summaryrefslogtreecommitdiffstats
path: root/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-191-4/+0
* soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons2022-05-051-1/+1
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-141-3/+0
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-141-0/+4
* drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman2021-12-231-4/+4
* soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer2021-12-091-3/+0
* soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer2021-12-091-1/+0
* soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer2021-08-281-1/+0
* mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA2021-08-161-2/+0
* mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA2021-08-161-3/+1
* mb/intel/tglrvp: Update Power Limit2 minimum valueSumeet Pawnikar2021-07-081-1/+1
* mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik2021-03-151-1/+7
* mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flagCliff Huang2021-03-151-1/+3
* mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh2020-11-021-4/+6
* tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak2020-10-301-2/+4
* mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner2020-10-261-3/+0
* mb/intel/tglrvp: Enable Pcie WWAN m.2Bora Guvendik2020-10-141-1/+1
* mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh2020-10-131-1/+1
* mb/intel/tglrvp: Add support of TPM over SPIShaunak Saha2020-10-121-6/+17
* mb/intel/tglrvp: Add DTT support for tglrvpSumeet R Pawnikar2020-09-281-1/+41
* mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVPShreesh Chhabbi2020-09-231-0/+3
* mb/intel/tglrvp: Enable HECI interfaceJamie Ryu2020-09-211-0/+3
* mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner2020-09-061-2/+0
* mb/tgl: Enable SaGv for TGL-UP3 RVPShreesh Chhabbi2020-08-101-1/+1
* mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons2020-08-041-3/+3
* mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configurationJohn Zhao2020-07-291-4/+0
* mb/intel/tglrvp: Add support for USB Type-C connector device propertiesJohn Zhao2020-07-291-1/+5
* mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4John Zhao2020-07-121-0/+3
* mb/intel/tglrvp: Enable CpuReplacementCheckJamie Ryu2020-07-121-0/+3
* mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik2020-07-091-2/+0
* mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3John Zhao2020-07-071-1/+22
* mb/intel/tglrvp: Add support for RT 1308Shaunak Saha2020-06-061-0/+6
* mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllersJohn Zhao2020-06-021-9/+10
* soc/intel/tigerlake: Disable VMDWonkyu Kim2020-05-261-1/+1
* mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvpJohn Zhao2020-05-261-0/+4
* soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak2020-05-201-1/+1
* soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik2020-04-201-6/+0
* mb/tglrvp: Configure intel common configWonkyu Kim2020-04-201-0/+20
* mb/intel/tglrvp : Enable RP LTRWonkyu Kim2020-04-141-0/+6
* src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS2020-04-101-2/+2
* tgl boards: Configure retimer Aux orientationBrandon Breitenstein2020-03-301-0/+3
* mb/tglrvp: Add GPE configurationShaunak Saha2020-03-301-0/+8
* mb/tglrvp: Update Audio AIC settings for Tiger LakeSrinidhi N Kaushik2020-03-231-1/+3
* mb/intel/tglrvp: Enable ISH driver and register firmware nameli feng2020-03-161-1/+6
* mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3Srinidhi N Kaushik2020-03-151-1/+1
* mb/intel/tglrvp: Enable Hybrid storage modeWonkyu Kim2020-03-111-0/+3
* mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik2020-03-101-1/+5
* mb/intel/tglrvp: Update display ports for RVPWonkyu Kim2020-03-071-0/+1
* mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGLSrinidhi N Kaushik2020-03-061-1/+44
* mb/intel/tglrvp: Enable DP ports for TGLRVPWonkyu Kim2020-01-281-0/+6
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-03 22:51:25 +0000