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* Move subsystem IDs to devicetree.cbStefan Reinauer2012-05-261-8/+0
* Clean up #ifsPatrick Georgi2012-05-081-1/+1
* Don't pre-enable SATA AHCI in romstage.cStefan Reinauer2012-05-031-3/+0
* ChromeOS: drop unused debug header descriptionStefan Reinauer2012-05-021-8/+0
* Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer2012-05-014-16/+0
* Clean up Emerald Lake 2 mainboard directoryGabe Black2012-05-013-6/+6
* Allow more CPU cores on Emerald Lake 2 CRBStefan Reinauer2012-05-011-1/+1
* Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.Gabe Black2012-05-013-30/+24
* Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer2012-05-013-11/+11
* Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.Gabe Black2012-05-011-1/+3
* Add support for Intel Emerald Lake 2 CRBStefan Reinauer2012-04-3028-0/+2836
* Move top level pc80 directory to drivers/Stefan Reinauer2012-04-272-2/+2
* Refactor some alignment handlingPatrick Georgi2012-04-203-3/+3
* cmos.layout: Remove invalid warningVikram Narayanan2012-04-151-3/+0
* Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki2012-03-161-1/+2
* Unify Local APIC address definitionsPatrick Georgi2012-03-086-6/+6
* Ati video: Apply un-written naming rulesKyösti Mälkki2012-02-241-1/+1
* ACPI: More ../../.. removalPatrick Georgi2012-02-221-4/+4
* intel/i82801cx: Move HAVE_HARD_RESET to southbridgePatrick Georgi2012-02-171-1/+0
* intel/i82801ex: Move HAVE_HARD_RESET to southbridgePatrick Georgi2012-02-171-1/+0
* Intel cpus: apply un-written naming rulesKyösti Mälkki2012-02-101-1/+1
* northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge2012-01-311-0/+1
* i3100: Add HAVE_HARD_RESETSven Schnelle2011-12-021-1/+0
* remove usbdebug.h include from mainboard/romstage codeSven Schnelle2011-10-301-1/+0
* Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi2011-10-281-1/+0
* Use default table creator macro for all SSDTsStefan Reinauer2011-10-131-2/+2
* mptable: Refactor mptable generation some morePatrick Georgi2011-10-136-34/+6
* mptable: Get rid of fixup_virtual_wirePatrick Georgi2011-10-136-6/+6
* mptable: Refactor lintsrc generationPatrick Georgi2011-10-136-18/+6
* Use ACPI text fields consistently with all other boardsStefan Reinauer2011-09-212-6/+6
* Add automatic SMBIOS table generationSven Schnelle2011-08-262-39/+0
* Remove old ACPI codeSven Schnelle2011-06-151-93/+0
* i82801gx: replace cafed00d/cafebabe by definesSven Schnelle2011-06-151-1/+1
* SMM: add defines for APM_CNT registerSven Schnelle2011-06-072-93/+84
* AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.Stefan Reinauer2011-05-231-1/+0
* run uart_init() from console_init, just like the other console initialization...Stefan Reinauer2011-04-207-8/+0
* * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer2011-04-181-5/+0
* fix mainboards that were including earlymtrr.c without actually using it.Stefan Reinauer2011-04-152-2/+0
* Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle2011-03-0111-40/+5
* [i945] Add SPD adress mappingSven Schnelle2011-02-211-1/+1
* Get mptable OEM/product ID from kconfig variables.Uwe Hermann2010-12-166-6/+6
* Compile cbmem.c instead of including it in romstage,Rudolf Marek2010-12-131-8/+0
* After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer2010-12-114-4/+4
* Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann2010-12-081-1/+0
* second round name simplification. drop the <component>_ prefix.stepan2010-12-087-8/+8
* first round name simplification. drop the <component>_ prefix.stepan2010-12-087-10/+10
* Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann2010-12-072-5/+0
* Drop per-board ram_check() calls for now.Uwe Hermann2010-11-224-23/+0
* Final set of smp_write_bus -> mptable_write_buses changes.Patrick Georgi2010-11-226-52/+12
* Simplify a few code chunks, fix whitespace and indentation.Uwe Hermann2010-11-215-23/+7
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