summaryrefslogtreecommitdiffstats
path: root/src/mainboard/intel
Commit message (Expand)AuthorAgeFilesLines
* sb/intel/lynxpoint/sata: Always use AHCI modeAngel Pons2020-11-101-2/+0
* mb/intel/adlrvp: Replace if-else-if ladder with switch constructSridhar Siricilla2020-11-091-5/+9
* mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvpV Sowmya2020-11-092-1/+32
* mb/intel/jasperlake_rvp: Update Power Limit2 minimum valueSumeet R Pawnikar2020-11-091-1/+1
* mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'Subrata Banik2020-11-0812-13/+17
* mb/intel/adlrvp: Configure GPIOs to enable DMICSridhar Siricilla2020-11-071-6/+6
* mb/intel: Enable ALC711 Audio codec over SNDW0 linkSridhar Siricilla2020-11-072-0/+6
* mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllersV Sowmya2020-11-071-7/+7
* mb/intel/adlrvp: Configure the HPD GPIO'sV Sowmya2020-11-071-0/+4
* mb/intel/adlrvp: Add support for DDR5 memorySubrata Banik2020-11-053-2/+21
* mb/intel/baskingridge: Convert to ASL 2.0 syntaxElyes HAOUAS2020-11-041-32/+32
* mb/intel/emeraldlake2: Convert to ASL 2.0 syntaxElyes HAOUAS2020-11-042-41/+41
* soc/intel/broadwell: Relocate PCH ACPI filesAngel Pons2020-11-031-2/+2
* mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh2020-11-0212-48/+72
* tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak2020-10-302-4/+8
* soc/intel/broadwell: Separate PCH in devicetreeAngel Pons2020-10-301-2/+2
* mb/intel/wtm2: Prepare devicetree for PCH splitAngel Pons2020-10-301-37/+40
* mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik2020-10-292-11/+24
* mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner2020-10-2612-35/+0
* soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner2020-10-217-217/+217
* superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons2020-10-191-1/+1
* mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik2020-10-161-0/+2
* mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik2020-10-161-1/+4
* mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik2020-10-161-2/+2
* mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik2020-10-161-0/+4
* mb/intel/adlrvp: Add ADL-P mainboard ASL codeSubrata Banik2020-10-141-0/+32
* mb/intel/adlrvp: Add ADL-P ramstage mainboard codeSubrata Banik2020-10-149-4/+594
* mb/intel/tglrvp: Enable Pcie WWAN m.2Bora Guvendik2020-10-144-2/+20
* {src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS2020-10-1324-24/+24
* mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh2020-10-1313-15/+15
* mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revisionElyes HAOUAS2020-10-131-1/+1
* mb/intel/latest mainboards: Get rid of power button device in corebootSubrata Banik2020-10-1310-70/+0
* mb/intel/d945gclf/acpi: Convert platform.asl to ASL 2.0 syntaxElyes HAOUAS2020-10-121-2/+2
* mb/intel: Convert to ASL 2.0 syntaxElyes HAOUAS2020-10-122-79/+77
* mb/intel/tglrvp: Enable early EC syncAnil Kumar2020-10-121-0/+1
* mb/intel/tglrvp: Add support of TPM over SPIShaunak Saha2020-10-125-13/+65
* mb/intel/adlrvp: Add ADL-P romstage mainboard codeSubrata Banik2020-10-1112-8/+296
* mb/intel/adlrvp: Add initial ADL-P mainboard codeSubrata Banik2020-10-0813-0/+397
* mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common'Subrata Banik2020-10-082-2/+0
* soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik2020-10-058-8/+8
* mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASLSubrata Banik2020-10-051-1/+1
* soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones2020-10-031-1/+1
* mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays...Jason Le2020-10-011-4/+14
* mb/intel/jslrvp: Update PMC as hidden deviceMaulik V Vaghela2020-09-291-1/+1
* mb/intel/tglrvp: Add DTT support for tglrvpSumeet R Pawnikar2020-09-283-2/+84
* mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVPShreesh Chhabbi2020-09-232-0/+6
* treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner2020-09-237-9/+9
* mb/*: drop GENERIC_SPD_BIN from boards without soldered memoryMichael Niewöhner2020-09-222-2/+0
* soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFNSumeet R Pawnikar2020-09-221-3/+0
* mb/intel/tglrvp: Enable CSE Firmware Lite SKUJamie Ryu2020-09-211-0/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 02:38:31 +0000