| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | {soc,vc,mb}/intel: Drop support for Cannon Lake SoC | Felix Singer | 2021-01-11 | 26 | -1281/+0 |
| * | mb/intel/adlrvp: Update GPIOs as per latest schematics | Subrata Banik | 2021-01-10 | 1 | -7/+7 |
| * | mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 | Subrata Banik | 2021-01-10 | 1 | -2/+8 |
| * | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik | 2021-01-10 | 1 | -7/+14 |
| * | soc/intel: Replace acpi_init_gnvs() | Kyösti Mälkki | 2021-01-10 | 2 | -4/+0 |
| * | mb/x/acpi_tables: Rename to mainboard_fill_gnvs() | Kyösti Mälkki | 2021-01-10 | 10 | -24/+8 |
| * | mb/x/acpi_tables: Move EC_RW detection | Kyösti Mälkki | 2021-01-10 | 2 | -10/+0 |
| * | pineview boards: Drop MAINBOARD_HAS_NATIVE_VGA_INIT | Angel Pons | 2021-01-08 | 1 | -1/+0 |
| * | mb/intel/jasperlake_rvp: Fix building with CONFIG_CHROMEOS unset | Matt DeVillier | 2021-01-07 | 1 | -1/+1 |
| * | mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unset | Matt DeVillier | 2021-01-07 | 1 | -1/+1 |
| * | soc/intel/broadwell: Move MAX_CPUS from mb to SoC | Felix Singer | 2021-01-06 | 1 | -5/+0 |
| * | soc/intel/skylake: Move MAX_CPUS from mb to SoC | Felix Singer | 2021-01-06 | 3 | -12/+0 |
| * | mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 | Angel Pons | 2021-01-06 | 1 | -1/+1 |
| * | cpu/intel/model_206ax: Rename `cX_acpower` options | Angel Pons | 2021-01-06 | 2 | -6/+6 |
| * | cpu/intel/model_206ax: Unify ACPI C-state options | Angel Pons | 2021-01-06 | 2 | -8/+0 |
| * | mb/intel/adlrvp: Make SI_ALL region within 16MiB | Subrata Banik | 2020-12-23 | 1 | -1/+1 |
| * | mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board | V Sowmya | 2020-12-21 | 5 | -0/+52 |
| * | mb/intel/coffeelake_rvp: Stop using headers for HDA verbs | Angel Pons | 2020-12-17 | 6 | -20/+1 |
| * | mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports | V Sowmya | 2020-12-17 | 1 | -0/+13 |
| * | mb/intel/tglrvp: Enable CNVi Bluetooth for UP4 | Bora Guvendik | 2020-12-14 | 1 | -1/+1 |
| * | soc/intel/braswell: Clean up devicetree settings | Angel Pons | 2020-12-14 | 1 | -10/+0 |
| * | soc/intel/skylake: Drop always-zero PowerLimit4 dt setting | Angel Pons | 2020-12-14 | 1 | -3/+0 |
| * | mb/intel/ehlcrb: Remove unrelated Kconfig settings | Tan, Lean Sheng | 2020-12-14 | 1 | -7/+0 |
| * | mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 | Subrata Banik | 2020-12-12 | 1 | -5/+5 |
| * | mb/intel/ehlcrb: Add EHL CRB memory initialization support | Tan, Lean Sheng | 2020-12-10 | 4 | -3/+96 |
| * | mb/intel/ehlcrb: Update ehl_crb device tree | Tan, Lean Sheng | 2020-12-10 | 1 | -186/+101 |
| * | mb/intel/ehlcrb: Remove JSL sku id info in SMBIOS | Tan, Lean Sheng | 2020-12-10 | 1 | -7/+0 |
| * | mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRB | Tan, Lean Sheng | 2020-12-10 | 3 | -118/+2 |
| * | mb/intel/ehlcrb: Remove board ID detection via EC | Tan, Lean Sheng | 2020-12-10 | 6 | -71/+1 |
| * | mb/intel/ehlcrb: Remove ChromeOS EC related headers | Tan, Lean Sheng | 2020-12-10 | 7 | -88/+0 |
| * | mb/intel/ehlcrb: Remove ChromeOS EC support from smihandler | Tan, Lean Sheng | 2020-12-10 | 2 | -38/+0 |
| * | mb/intel/ehlcrb: Remove ChromeOS support from mainboard | Tan, Lean Sheng | 2020-12-10 | 7 | -98/+0 |
| * | mb/intel/ehlcrb: Add missing 'include <console/console.h>' | Tan, Lean Sheng | 2020-12-10 | 1 | -0/+1 |
| * | mb/intel/ehlcrb: Add initial mainboard code | Tan, Lean Sheng | 2020-12-10 | 23 | -0/+917 |
| * | mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2 | V Sowmya | 2020-12-09 | 1 | -1/+9 |
| * | mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB | Furquan Shaikh | 2020-12-08 | 1 | -2/+2 |
| * | mb/intel/adlrvp: Remove GPP_E0 | Meera Ravindranath | 2020-12-07 | 1 | -2/+0 |
| * | mb/*: Remove unnecessary selects | Felix Singer | 2020-12-06 | 1 | -1/+0 |
| * | cbfs: Simplify load/map API names, remove type arguments | Julius Werner | 2020-12-02 | 2 | -4/+2 |
| * | mb/intel/adlrvp: Replace tab by white space in devicetree | Meera Ravindranath | 2020-12-02 | 1 | -1/+1 |
| * | mb/intel/jslrvp: Modify the flash layout for fsp debug build | V Sowmya | 2020-12-01 | 1 | -24/+25 |
| * | mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP | Subrata Banik | 2020-12-01 | 2 | -6/+0 |
| * | mb/intel/adlrvp: Add ASL support for WFC annd UFC | Varshit Pandya | 2020-12-01 | 2 | -0/+502 |
| * | mb/intel/adlrvp: Configure Camera related GPIO as per schematics | Varshit Pandya | 2020-12-01 | 1 | -11/+8 |
| * | mb/intel/adlrvp: Update GPIO configuration as per schematics | Varshit Pandya | 2020-12-01 | 1 | -30/+10 |
| * | mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot | Subrata Banik | 2020-12-01 | 2 | -1/+11 |
| * | mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU | Subrata Banik | 2020-12-01 | 1 | -3/+3 |
| * | mb/intel/adlrvp: Add support for LPDDR5 | Sridhar Siricilla | 2020-12-01 | 5 | -4/+71 |
| * | mb/intel/adlrvp: Refactor lpddr4_mem_config structure | Subrata Banik | 2020-12-01 | 1 | -19/+9 |
| * | mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP | Subrata Banik | 2020-11-29 | 1 | -2/+2 |
