index
:
coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
coreboot-v1
coreboot-v3
main
master
rampayload
Coreboot firmware sources
coreboot
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path:
root
/
src
/
mainboard
/
ocp
/
tiogapass
/
dsdt.asl
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location
Shuo Liu
2024-05-06
1
-2
/
+2
*
mb/**/dsdt.asl: Drop misleading "OEM revision" comment
Angel Pons
2022-08-16
1
-1
/
+1
*
ACPI: Add top-level ASL
Kyösti Mälkki
2021-01-27
1
-0
/
+1
*
soc/intel/xeon_sp/nvs: Use common global NVS
Marc Jones
2020-12-10
1
-1
/
+1
*
mainboard/ocp/tiogapass: Add xeon_sp pch.asl
Marc Jones
2020-11-07
1
-0
/
+4
*
mb/ocp/tiogapass/dsdt: Remove unnecessary comments
Maxim Polyakov
2020-10-28
1
-4
/
+0
*
mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scope
Maxim Polyakov
2020-10-28
1
-5
/
+1
*
{src/mb,util/autoport}: Use macro for DSDT revision
Elyes HAOUAS
2020-10-13
1
-1
/
+1
*
soc/intel/xeon_sp: Use common ASL code for xeon_sp
Marc Jones
2020-10-03
1
-2
/
+2
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
treewide: replace GPLv2 long form headers with SPDX header
Patrick Georgi
2020-05-06
1
-12
/
+1
*
treewide: Move "is part of the coreboot project" line in its own comment
Patrick Georgi
2020-05-06
1
-2
/
+1
*
acpi: Move ACPI table support out of arch/x86 (3/5)
Furquan Shaikh
2020-05-02
1
-1
/
+1
*
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Andrey Petrov
2020-03-26
1
-2
/
+2
*
mainboard/[g-p]*: Remove copyright notices
Patrick Georgi
2020-03-18
1
-2
/
+0
*
mainboard/ocp: Add support for OCP platform TiogaPass
Jonathan Zhang
2020-03-06
1
-0
/
+41
