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coreboot.git
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path:
root
/
src
/
mainboard
/
pcengines
/
apu2
/
variants
/
apu2
/
devicetree.cb
Commit message (
Expand
)
Author
Age
Files
Lines
*
nb/amd/pi/00730F01: restructure chip ops
Felix Held
2023-11-17
1
-9
/
+7
*
nb/amd/pi/00730F01: introduce and use chipset devicetree
Felix Held
2023-11-17
1
-36
/
+17
*
mb/*: Remove lapic from devicetree
Arthur Heymans
2023-01-30
1
-5
/
+1
*
src: Remove leading blank lines from SPDX header
Elyes HAOUAS
2020-05-18
1
-3
/
+0
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
src/: Replace GPL boilerplate with SPDX headers
Patrick Georgi
2020-05-09
1
-9
/
+2
*
superio/nuvoton/nct5104d: add chip config option to reset GPIOs
Michał Żygowski
2020-03-25
1
-0
/
+1
*
mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe
Michał Żygowski
2020-03-25
1
-1
/
+0
*
mainboard/[g-p]*: Remove copyright notices
Patrick Georgi
2020-03-18
1
-1
/
+0
*
mb/pcengines/*: enable simple IO-based GPIO control
Piotr Kleinschmidt
2020-01-20
1
-1
/
+4
*
mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset
Piotr Kleinschmidt
2020-01-15
1
-1
/
+1
*
binaryPI: Drop nested northbridge in devicetree
Kyösti Mälkki
2019-02-12
1
-64
/
+62
*
pcengines/apu2: enable IOMMU for all apu2 variants
Piotr Król
2018-09-15
1
-1
/
+1
*
mainboard/pcengines/apu2: add apu3 and apu5 variants
Kamil Wcislo
2017-10-20
1
-0
/
+94