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path: root/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer2023-06-191-1/+1
* soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer2023-06-021-2/+2
* mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA portsMario Scheithauer2023-06-011-0/+2
* mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2Mario Scheithauer2023-06-011-0/+1
* soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans2023-02-031-2/+0
* mb/*: Remove lapic from devicetreeArthur Heymans2023-01-301-3/+1
* soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes2022-06-201-0/+2
* mb/siemens/mc_apl2: Enable PCI device for I2C bus 0Werner Zeh2022-02-221-1/+1
* mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM supportMario Scheithauer2022-02-011-1/+3
* mb/siemens/mc_apl2: Disable unused I2C controllersWerner Zeh2021-06-041-7/+7
* mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHzWerner Zeh2021-06-041-1/+7
* mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequencyWerner Zeh2021-05-021-0/+10
* mb/siemens/mc_apl2: Switch I2C bus for RX6110SAMario Scheithauer2021-02-101-4/+4
* mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDsMario Scheithauer2021-01-201-15/+24
* apollolake boards: Enable CSE in devicetreeSubrata Banik2020-09-191-0/+1
* mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer2019-07-111-1/+1
* mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variantsWerner Zeh2019-04-151-1/+1
* siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer2019-02-131-1/+0
* mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh2019-02-051-0/+3
* siemens/mc_apl2: Change SERIRQ modeMario Scheithauer2019-01-301-1/+0
* siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer2019-01-301-10/+10
* siemens/mc_apl2: Activate TPM supportMario Scheithauer2019-01-301-0/+5
* siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer2018-09-271-0/+109