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* soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer2023-06-191-1/+1
| | | | | | | | | | | For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer2023-06-021-2/+2
| | | | | | | | | | | | | For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
* mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA portsMario Scheithauer2023-06-011-0/+2
| | | | | | | | | | | | | | There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
* mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2Mario Scheithauer2023-06-011-0/+1
| | | | | | | | | | | | Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans2023-02-031-2/+0
| | | | | | | | | Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/*: Remove lapic from devicetreeArthur Heymans2023-01-301-3/+1
| | | | | | | | | | | | The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes2022-06-201-0/+2
| | | | | | | | | | | | Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl2: Enable PCI device for I2C bus 0Werner Zeh2022-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus devices (16.0, 16.1 and 16.2) have been disabled as they are not used. While coreboot can handle the case where a PCI device does not have function 0 enabled but a later one (here function 3), Linux seems to check for function 0 first and ignores the rest if function 0 is missing. So enable PCI device 16.0 in order to let Linux use 16.3 again. Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are visible and I2C attached RTC works properly. Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM supportMario Scheithauer2022-02-011-1/+3
| | | | | | | | | | | | | | | Aggressive Link Power Management are no longer supported on these mainboards and must therefore be disabled. This feature can have a negative impact on the real-time behavior of the systems. TEST: - Boot into system software on mc_apl1 Change-Id: I8b08381743018790a20273ea1f61e5b0a56e6015 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl2: Disable unused I2C controllersWerner Zeh2021-06-041-7/+7
| | | | | | | | | | | | Only I2C controller 3 is used on this mainboard. Disable all other controllers. Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHzWerner Zeh2021-06-041-1/+7
| | | | | | | | | | | | | | | The I2C bus at which the external RTC is attached to is operated at standard speed (100 kHz) at coreboot runtime. The OS can choose to run it at fast speed since it uses its own driver and controller setup. Report additional bus timings for fast mode so that OS can do it right. Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequencyWerner Zeh2021-05-021-0/+10
| | | | | | | | | | | | | | | | | | | All the boards in the patch have a constraint for the I2C bus to operate on 100 kHz. Provide dedicated values for rise time, fall time and data hold time on mainboard level to get a proper timing which takes the bus load into account. Giving these values the driver computes the needed timings correctly. TEST=Measure I2C frequency on all boards while coreboot accesses external RTC and make sure it is 100 kHz. Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl2: Switch I2C bus for RX6110SAMario Scheithauer2021-02-101-4/+4
| | | | | | | | | | | | With a new HW revision of this board, the connection of the external RTC RX6110SA was changed from I2C bus 0 to I2C bus 3. Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDsMario Scheithauer2021-01-201-15/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Until now some FSP-S parameters were configured for Siemens APL mainboards via the Binary Configuration Tool (BCT). For simplification, the original APL FSP binary should now be used. For this purpose, the corresponding FSP-S parameters are set via devicetree, respectively via mainboard_silicon_init_params accordingly. The following parameters are affected: - Disable CPU power states (C-states) - Set lowest Max Pkg Cstate - PkgC0C1 - Disable PCIe Hot Plug for all enabled RPs - Disable PCIe Transmitter Half Swing for all RPs - Disable PCIe Active State Power Management (ASPM) for all RPs - Disable PCIe L1 Substates for all RPs TEST: - Compare old with new coreboot log on mc_apl5, found no differences - Boot Linux v4.4 and check output of 'lspci' Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* apollolake boards: Enable CSE in devicetreeSubrata Banik2020-09-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer2019-07-111-1/+1
| | | | | | | | | | | We need to reduce the eMMC bus speed for these Apollo Lake mainboards because of a limitation on Intel side for industry use cases. Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variantsWerner Zeh2019-04-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | With commit '4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)' FSP is now requested to switch off HDA PCI device if it is disabled in devicetree. Doing so results in a warm restart. Normally this event will be stored in CMOS RAM (if the descriptor is configured to do so) and therefore no further resets are requested by FSP on the next boots as long as CMOS RAM is kept alive. The Siemens mainboards based on Apollo Lake do not have a CMOS battery and therefore the CMOS is not backed up. This leads to reset requests from FSP after PCI enumeration on every boot. To avoid this reset enable HDA in devicetree for these mainboards. Though we do not have any usage of HDA it should not be an issue that the HDA device is now enabled. The benefit is though that no reset is requested anymore by FSP. Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer2019-02-131-1/+0
| | | | | | | | | | | | Remove a double entry for LPC device from devicetree. Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh2019-02-051-0/+3
| | | | | | | | | | These boards need a working VTD therefore enable this feature. Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* siemens/mc_apl2: Change SERIRQ modeMario Scheithauer2019-01-301-1/+0
| | | | | | | | | | | | | | Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47. Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31138 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer2019-01-301-10/+10
| | | | | | | | | | Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* siemens/mc_apl2: Activate TPM supportMario Scheithauer2019-01-301-0/+5
| | | | | | | | | | | | | | | | | The TPM chip is connected to the SPI interface of APL. The proper chip select pin needs to be used in order to access the TPM in the memory mapped space. This needed chip select is internally (inside APL) routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to make the TPM work on SPI bus. TEST=Build coreboot for mc_apl2 board and check the TPM console output. In addition the TPM was correctly verified by our Linux driver. Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer2018-09-271-0/+109
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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