summaryrefslogtreecommitdiffstats
path: root/src/mainboard/siemens/mc_ehl
Commit message (Expand)AuthorAgeFilesLines
* mb/siemens/mc_ehl: Disable RAPLUwe Poeche2022-05-231-0/+1
* mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer2022-05-211-0/+3
* mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan2022-05-201-2/+0
* mainboard/**/devicetree.cb: Fix typoAngel Pons2022-05-172-2/+2
* soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons2022-05-172-2/+0
* mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer2022-05-171-0/+8
* mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer2022-05-161-0/+1
* mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer2022-05-161-1/+1
* mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer2022-05-161-0/+4
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-211-1/+1
* mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytesWerner Zeh2022-03-141-2/+2
* src: Make PCI ID define names shorterFelix Singer2022-03-071-2/+2
* mb/siemens/mc_ehl: Disable HS400 mode for eMMCWerner Zeh2022-03-022-2/+2
* mb/siemens/mc_ehl2: Disable PCIe RPsMario Scheithauer2022-02-031-16/+4
* mb/siemens/mc_ehl2: Disable SATAMario Scheithauer2022-02-031-9/+1
* mb/siemens/mc_ehl: Prevent reset when TCO expiresWerner Zeh2022-01-251-0/+3
* soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-212-6/+0
* src/mainboard/{siemens,starlabs}: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
* mb: Add space before closing comment block keywordPaul Menzel2021-12-231-1/+1
* mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh2021-12-101-0/+1
* mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCIWerner Zeh2021-11-173-0/+28
* mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer2021-11-151-2/+2
* mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer2021-11-152-2/+0
* mb/siemens/mc_ehl: Disable PMC low power modesWerner Zeh2021-11-041-0/+5
* mb/siemens/mc_ehl: Disable all P-StatesWerner Zeh2021-11-041-0/+3
* mb/siemens/mc_ehl: Disable C-States for CPU and packageWerner Zeh2021-11-041-0/+10
* mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer2021-11-041-64/+4
* mb/siemens/mc_ehl: Enable Row-Hammer preventionMario Scheithauer2021-11-041-0/+3
* mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer2021-11-041-0/+3
* mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer2021-11-041-8/+2
* mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer2021-11-041-13/+13
* mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh2021-11-031-13/+13
* mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh2021-11-021-8/+2
* mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh2021-11-021-74/+4
* mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer2021-10-141-17/+6
* mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer2021-10-141-12/+12
* mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer2021-10-141-4/+4
* mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer2021-10-141-0/+11
* mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh2021-10-121-4/+1
* mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh2021-10-121-3/+22
* mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer2021-10-112-0/+14
* mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer2021-10-112-0/+11
* mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer2021-10-111-0/+1
* mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer2021-10-111-1/+0
* mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer2021-10-111-54/+35
* mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer2021-10-111-17/+23
* mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer2021-10-111-3/+3
* mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh2021-10-013-5/+8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 09:30:42 +0000