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* mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu2023-03-054-0/+54
| | | | | | | | | | | | | | | | | | | | Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/geralt: Add mtcmos bus protection for displayLiju-Clr Chen2023-03-051-0/+1
| | | | | | | | | | | | | | | | | Enable bus protection for display to avoid bus hang and incomplete bus transaction. BUG=b:264204465 TEST=test firmware and kernel display pass for MIPI panel on geralt. Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73411 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/hades: Add baseboard device treeEric Lai2023-03-051-0/+120
| | | | | | | | | | | | | | Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su2023-03-043-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu2023-03-041-0/+23
| | | | | | | | | | | | | | | | | According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang2023-03-044-14/+1
| | | | | | | | | | | | | | | | The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/system76/adl-p: Add Oryx Pro 10 as a variantTim Crawford2023-03-049-4/+657
| | | | | | | | | | | | | | oryp10 is nearly identical to the oryp9, with the differences being: - Uses DDR5 RAM instead of DDR4 RAM - Uses Realtek ALC1306 instead of TI TAS5825M - Has an option for OLED display Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/adl: Add Oryx Pro 9 as a variantTim Crawford2023-03-0411-2/+1745
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Oryx Pro 9 (oryp9) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - Both M.2 NVME SSD slots (with MZVL2500HCJQ) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - Discrete/Hybrid graphics - HDMI output (requires NVIDIA GPU) - Mini DisplayPort output (requires NVIDIA GPU) - Detection of devices in TBT slot on boot Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/adl: Add Lemur Pro 11 as a variantTim Crawford2023-03-0411-1/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dtScott Chao2023-03-041-0/+11
| | | | | | | | | | | | | BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76: Add custom backlight levels for Intel GMATim Crawford2023-03-0423-7/+273
| | | | | | | | | | | | | Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/tgl-u: Leave TBT LSX0 as FSP configuredTim Crawford2023-03-043-6/+6
| | | | | | | | | | Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* {ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford2023-03-0410-60/+0
| | | | | | | | | | | Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/google/brya: remove the skolas baseboardNick Vaccaro2023-03-049-898/+6
| | | | | | | | | | | | | | | | | | The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth2023-03-031-4/+0
| | | | | | | | | | | | | | | This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacksJan Samek2023-03-035-15/+15
| | | | | | | | | | | | | | | | | | | | As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mainboard/protectli/vault_ehl: Add initial structureKacper Stojek2023-03-0313-0/+2096
| | | | | | | | | | | | | | | | This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* mb/google/rex: Enable VPURavi Sarawadi2023-03-021-0/+1
| | | | | | | | | | | | BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes2023-03-021-3/+4
| | | | | | | | | | Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten2023-03-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/siemens/mc_ehl*: Correct comment in gpio.cMario Scheithauer2023-03-023-6/+6
| | | | | | | | | | | There were two wrong comments in all mc_ehl gpio.c files. This patch corrects the incorrect comments. Change-Id: Iea356db177227d89b91be32a4e2367c612b77350 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72458 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl4: Remove TPM from devicetree and KconfigMario Scheithauer2023-03-022-9/+1
| | | | | | | | | | This mainboard does not use security features like TPM. Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Move TPM Kconfig switches to variantsMario Scheithauer2023-03-025-4/+16
| | | | | | | | | | | | | The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard without a TPM. For this reason, the corresponding Kconfig switches must be moved to variant level. To prevent Jenkins build from complaining, the TPM is removed in the following patch. Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Set RGMII output impedance manuallyMario Scheithauer2023-03-021-0/+6
| | | | | | | | | | | | Measurements have shown that the automatic calibrated values for RGMII output impedances are too low. For this reason, set the PMOS value to 16 and the NMOS to 13. Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1Mario Scheithauer2023-03-028-0/+484
| | | | | | | | | | | | This mainboard is based on mc_ehl1. In a first step, it contains a copy of mc_ehl1 directory with minimum changes. Special adaptations for mc_ehl4 mainboard will follow in separate commits. Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Fix GPIO settingsMario Scheithauer2023-03-021-2/+2
| | | | | | | | | | | | | | | With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are no longer connected to a native function. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik2023-03-023-0/+3
| | | | | | | | | | | | | | | | | Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik2023-03-023-1/+3
| | | | | | | | | | | | | | | | | Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/brask/var/constitution: Enable Fast VMode for constitutionMorris Hsu2023-03-021-0/+4
| | | | | | | | | | | | | | | Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Remove extra DC boost byteTarun Tuli2023-03-011-1/+1
| | | | | | | | | | | | | | | | The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 sJan Samek2023-03-011-2/+2
| | | | | | | | | | | | | | | | The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. BUG=none TEST=Test link stability using a panel with minimum re-power delay of 1 s. Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/amd/gardenia,pademelon/mainboard: use ACPI_SCI_IRQ definitionFelix Held2023-02-282-2/+4
| | | | | | | | | | | | | | Use the ACPI_SCI_IRQ definition for both the PIC and APIC IRQ number in the fch_irq_map table. Before the PIC mapping was set to PIRQ_NC, but both mb/google/kahlee and the other amd mainboards using newer SoCs set both the PIC and APCI IRQ number to ACPI_SCI_IRQ, so change this here to match the other mainboards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29dde7ca8d2ecf00d8174c2d793ef1ad55ae3e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73322 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee/mainboard: use ACPI_SCI_IRQ definitionFelix Held2023-02-281-1/+2
| | | | | | | | | | Use the ACPI_SCI_IRQ definition instead of a magic value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76: Rename adl-p to adlTim Crawford2023-02-2828-1/+1
| | | | | | | | | | The directory holds boards other than ADL-P, such as ADL-U and ADL-H. Change-Id: I8e1b67f83d649cd07645a4a519ba1bf2f6f5e7c6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/google/skryim: Add RECOVERY_MRC_CACHE FMAP sectionKarthikeyan Ramasubramanian2023-02-272-0/+2
| | | | | | | | | | | | | | | | | Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP section to cache the MRC training data in recovery mode. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the appropriate MRC_CACHE FMAP section. Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/skyrim/var/winterhold: Use fw_config to probe FPEricKY Cheng2023-02-272-2/+18
| | | | | | | | | | | | | | Use fw_config to probe fingerprint. BUG=b:269986245 TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass with 1000 reboot cycles. Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/brya/var/osiris: Enable Fast VMode for osirisDavid Wu2023-02-271-0/+4
| | | | | | | | | | | | | | | | | Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/osiris: use RPL FSP headersDavid Wu2023-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | To support an RPL SKU on osiris, osiris must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL FSP headers for osiris. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot osiris to kernel. Cq-Depend: chromium:4290627, chrome-internal:5516851 Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/nissa/var/xivu: Disable world-facing microphoneIan Feng2023-02-272-4/+4
| | | | | | | | | | | | | | | | | | Remove world-facing microphone for xivu360. Switching to world-facing camera will use the user-facing microphone to record sound. BUG=b:263927799 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
* mb/google/dedede/var/dibbi: Improve USB2 strengthAmanda Huang2023-02-271-4/+40
| | | | | | | | | | | | BUG=b:269786649 TEST=build and test USB2 port function works fine BRANCH=dedede Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/brask/var/constitution: use RPL FSP headersMorris Hsu2023-02-271-0/+1
| | | | | | | | | | | | | | | | | To support an RPL SKU on constitution, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL FSP headers. BUG=b:267539938 TEST=emerge-brask intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246 Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brask/var/constitution: Update overridetreeMorris Hsu2023-02-271-1/+299
| | | | | | | | | | | | | | | Update override devicetree based on schematics. BUG=None TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I883a806950821e6306242975764930035a94888e Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google/rex: Remove `fixme` from gpio.hKapil Porwal2023-02-271-1/+0
| | | | | | | | | | | | | | Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/amd/birman/bootblock.c: Skip EC configuration in SimNowFred Reitberger2023-02-271-1/+2
| | | | | | | | | | | SimNow does not support the Birman EC, so skip the EC configuration steps when building for SimNow. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6e879a13a119d593674d3403d4e1b32e0e244d9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/birman,chausie: Enable SimNow capabilitiesFred Reitberger2023-02-272-6/+8
| | | | | | | | Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia7e594ca2b6ea3cd9d6f60e7dcd1ba6ebabf85cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim/var/winterhold: Remove gpio-keys ACPI node for PENHEricKY Cheng2023-02-242-24/+0
| | | | | | | | | | | | | | | | Remove ACPI node for pen eject event to meet project design. BUG=b:265106657 TEST=emerge-skyrim coreboot chromeos-bootimage Change-Id: I732de49c6319397d93671c48a6518c7c7e955fdc Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73154 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/var/crystaldrift: Generate RAM IDs for new memory partsYunlong Jia2023-02-244-0/+29
| | | | | | | | | | | | | | | | | | | | | Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 3 (0011) BUG=b:265190498 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/google/brya/var/gladios: Update gpio table"Robert Chen2023-02-241-1/+5
| | | | | | | | | | | | | This reverts commit 3eb17b91daac0b3acaffb01568d724d23c6f0eea. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: If4277cb600bfe4e071959dacaf204fe7d3518f68 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73202 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* Revert "mb/google/brya/var/lisbon: Update gpio table"Robert Chen2023-02-241-1/+5
| | | | | | | | | | | | | | This reverts commit 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brask/var/constitution: update gpio settingsMorris Hsu2023-02-241-3/+5
| | | | | | | | | | | | | | | Update GPP_E12,GPP_E13,GPP_H19 in ramstage. Update GPP_F11 in bootblock. TEST=emerge-brask coreboot Change-Id: Icdca7f574282da140ec64cea9cdda3ebccbe3eb8 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73194 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 20:05:23 +0000