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path: root/src/northbridge/intel/haswell/haswell.h
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* haswell/lynxpoint: Add native DMI initAngel Pons2022-12-161-0/+3
* nb/intel/haswell: Move PEG registers to a separate headerAngel Pons2021-05-031-29/+1
* nb/intel/haswell: Uniformize include guardsAngel Pons2021-05-021-3/+3
* nb/intel/haswell: Clean up haswell.h headerAngel Pons2021-05-021-36/+6
* nb/intel: Factor out remaining MCHBAR macrosAngel Pons2021-04-101-10/+0
* nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`Angel Pons2021-03-281-4/+0
* nb/intel/haswell: Finalize northbridge in ramstageAngel Pons2021-03-101-2/+0
* nb/intel/haswell/pcie.c: Add missing pre-ASPM initAngel Pons2021-03-101-0/+21
* nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-121-11/+4
* nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons2021-01-301-2/+0
* nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons2021-01-271-2/+0
* nb/intel/haswell/gma.c: Drop unused `set_translation_table` functionAngel Pons2020-10-251-1/+0
* nb/intel/haswell: Set up Root Complex topologyAngel Pons2020-10-241-0/+10
* src/northbridge: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
* nb/intel/haswell: Put DMIBAR/EPBAR registers into separate filesAngel Pons2020-09-171-66/+2
* nb/intel/haswell: Move register headers into a subfolderAngel Pons2020-09-171-2/+2
* nb/intel/haswell: Clean up register definitionsAngel Pons2020-09-171-12/+17
* nb/intel/haswell: Guard DMIBAR/EPBAR macro parametersAngel Pons2020-09-171-6/+6
* nb/intel/haswell: Introduce memmap.hAngel Pons2020-09-171-13/+1
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-041-0/+2
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-281-0/+10
* nb/intel/haswell: Put host bridge registers into its own fileAngel Pons2020-07-241-60/+9
* haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons2020-07-121-2/+0
* haswell: Drop `struct romstage_params` typeAngel Pons2020-07-121-4/+1
* haswell: Make `copy_spd` a weak functionAngel Pons2020-07-121-1/+0
* nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons2020-07-111-0/+1
* haswell: Drop GPIO indirection layersAngel Pons2020-07-091-1/+0
* haswell: Turn RCBA configuration into a functionAngel Pons2020-07-091-2/+0
* haswell: relocate `romstage_common` to northbridgeAngel Pons2020-07-081-0/+10
* haswell: drop unused function parameterAngel Pons2020-07-081-1/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh2020-04-281-1/+1
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
* nb/intel/haswell: Tidy up code and commentsAngel Pons2020-03-151-35/+33
* nb/intel: Remove unused 'barrier()'Elyes HAOUAS2019-11-011-1/+0
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-011-4/+0
* nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki2019-09-281-5/+1
* intel/smm: Define struct ied_header just onceKyösti Mälkki2019-08-151-6/+0
* Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki2019-03-061-1/+0
* Drop leftover debug function declarationsKyösti Mälkki2019-01-231-5/+0
* {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS2019-01-131-1/+0
* nb/intel/haswell: Add support for PEGTristan Corrick2019-01-031-0/+1
* nb/intel/haswell: Handle boards that do not support IGDTristan Corrick2018-12-291-0/+5
* nb/intel/haswell: Consolidate memory controller PCI driver structsTristan Corrick2018-11-021-4/+0
* nb/intel/haswell: Add a PCI ID for a desktop memory controllerTristan Corrick2018-11-011-0/+1
* Move compiler.h to commonlibNico Huber2018-10-081-1/+0
* nb/intel/haswell: Get rid of device_tElyes HAOUAS2018-05-181-1/+1
* nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier2018-03-081-0/+18
* nb/intel/haswell: Generate ACPI DMAR tableMatt DeVillier2018-03-081-0/+8
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