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* nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons2020-08-041-3/+3
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-35/+11
* nb/intel/haswell: Add Crystal Well PCI IDsIru Cai2020-08-034-3/+15
* nb/intel/haswell: Configure VCs on Egress PortAngel Pons2020-07-311-0/+17
* nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph2020-07-302-0/+52
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-282-0/+52
* src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth2020-07-261-2/+2
* nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS2020-07-261-1/+1
* nb/intel/haswell/hostbridge_regs.h: Clean up registersAngel Pons2020-07-251-6/+13
* nb/intel/haswell: Put host bridge registers into its own fileAngel Pons2020-07-242-60/+69
* sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons2020-07-201-1/+1
* nb/intel/haswell/romstage.c: Align pei_data initializersAngel Pons2020-07-121-19/+19
* haswell: Move some MRC settings to devicetreeAngel Pons2020-07-122-0/+12
* haswell: Automatically check if Intel GbE is to be enabledAngel Pons2020-07-121-0/+4
* haswell: Add function to retrieve SPD addressesAngel Pons2020-07-122-0/+7
* haswell: Automatically determine system typeAngel Pons2020-07-121-0/+1
* haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons2020-07-122-0/+9
* haswell: Factor out `max_ddr3_freq`Angel Pons2020-07-121-0/+1
* haswell: Compute disabled channel masks at runtimeAngel Pons2020-07-121-0/+15
* mb/asrock/b85m_pro4: Factor out common MRC settingsAngel Pons2020-07-121-0/+12
* haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons2020-07-123-8/+16
* haswell: Drop `struct romstage_params` typeAngel Pons2020-07-122-10/+7
* haswell: Make `copy_spd` a weak functionAngel Pons2020-07-123-3/+9
* nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons2020-07-112-0/+7
* haswell: Drop GPIO indirection layersAngel Pons2020-07-092-2/+1
* haswell: Turn RCBA configuration into a functionAngel Pons2020-07-092-3/+1
* haswell: relocate `romstage_common` to northbridgeAngel Pons2020-07-083-0/+92
* haswell: drop unused function parameterAngel Pons2020-07-082-2/+2
* nb/intel/haswell/acpi: Update to ASL 2.0 syntaxAngel Pons2020-07-081-4/+4
* nb/intel/haswell/acpi: Fix host bridge registersAngel Pons2020-07-081-6/+5
* nb/intel/haswell: Use 16-bit ops on PCI COMMANDAngel Pons2020-06-221-1/+1
* nb/intel/haswell: Use PCI bitwise opsAngel Pons2020-06-092-7/+2
* src: Use pci_dev_ops_pci where applicableAngel Pons2020-06-064-20/+4
* src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS2020-06-061-1/+0
* northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge...Furquan Shaikh2020-06-031-2/+6
* northbridge/intel/haswell: Update hostbridge.asl to ASL2.0Furquan Shaikh2020-06-031-41/+40
* intel/gma: Only enable bus mastering if we are going to use itNico Huber2020-05-271-6/+3
* intel/gma: Don't bluntly enable I/ONico Huber2020-05-271-1/+1
* drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber2020-05-271-42/+2
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel2020-05-121-5/+0
* treewide: Replace BSD-3-Clause and ISC headers with SPDX headersPatrick Georgi2020-05-111-23/+1
* treewide: split off license text, remove extra copyright noticesPatrick Georgi2020-05-111-5/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1120-20/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()Julius Werner2020-05-091-1/+2
* nb/intel/haswell/northbridge.c: Fix typoAngel Pons2020-05-081-1/+1
* northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-081-13/+2
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-022-2/+2
* nb/intel/haswell/pei_data.h: Add ULT system typeAngel Pons2020-04-291-1/+2
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