coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT	Martin Roth	2018-01-15	1	-693/+0
*	northbridge/intel/i3100: Add space around operators	Elyes HAOUAS	2016-09-20	1	-1/+1
*	src/northbridge: Improve code formatting	Elyes HAOUAS	2016-09-12	1	-1/+1
*	northbridge/intel/i3100: Unify UDELAY selection	Stefan Reinauer	2016-03-13	1	-0/+1
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	lib: Unify log2() and related functions	Julius Werner	2015-06-05	1	-0/+1
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-1/+1
*	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert	2015-02-15	1	-2/+2
*	northbridge: Drop print_ implementation from non-romcc boards	Stefan Reinauer	2015-01-06	1	-130/+50
*	intel/truxton: Un-romcc-ify board	Stefan Reinauer	2014-12-18	1	-10/+3
*	src: Make use of 'CEIL_DIV(a, b)' macro across tree	Edward O'Callaghan	2014-07-11	1	-5/+5
*	northbridge/intel/i3100/raminit.c: Uninitialized variable	Edward O'Callaghan	2014-05-25	1	-2/+2
*	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel	2013-03-01	1	-1/+1
*	Intel: Replace MSR 0xcd with MSR_FSB_FREQ	Patrick Georgi	2013-02-11	1	-2/+3
*	Rename cache_lbmem() to cache_ramstage()	Stefan Reinauer	2012-07-24	1	-1/+1
*	Move C labels to start-of-line	Patrick Georgi	2012-03-07	1	-1/+1
*	Replace while with do; while to avoid repetition	Noe Rubinstein	2011-09-09	1	-36/+24
*	Convert some comments to proper Doxygen syntax.	Uwe Hermann	2010-10-26	1	-1/+0
*	Since some people disapprove of white space cleanups mixed in regular commits	Stefan Reinauer	2010-04-27	1	-28/+28
*	Drop \r\n and \n\r as both print_XXX and printk now do this internally.	Stefan Reinauer	2010-03-31	1	-61/+61
*	Replace clear_memory with memset.	Myles Watson	2010-03-11	1	-1/+0
*	This patch adds VGA and PS/2 Keyboard/mouse support to the already existing i...	Arnaud Maye	2009-08-28	1	-1/+1
*	Support for the memory controller and PCIe interface of the Intel	Ed Swierk	2008-09-24	1	-0/+795