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path: root/src/northbridge/intel/ironlake/early_init.c
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* nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons2022-02-241-4/+0
* nb/intel/ironlake: Use new fixed BAR accessorsAngel Pons2021-04-101-2/+2
* nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-101-6/+6
* nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons2020-12-071-2/+2
* nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons2020-08-031-1/+1
* nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons2020-08-031-1/+1
* nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons2020-08-031-7/+7
* nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons2020-08-031-1/+1
* nb/intel/ironlake: Move southbridge code to ibexpeakAngel Pons2020-07-241-19/+1
* nb/intel/ironlake: Clean up code style (except raminit)Angel Pons2020-07-021-7/+5
* nb/intel/ironlake: Use `pci_update_config32()`Angel Pons2020-07-011-2/+1
* nb/intel/ironlake: Simplify BAR handlingAngel Pons2020-07-011-7/+3
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-3/+0
* nb/intel/nehalem: Rename to ironlakeAngel Pons2020-03-151-0/+158
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