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path: root/src/northbridge/intel/sandybridge/raminit_ivy.c
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* nb/intel/sandybridge: Rename raminit_ivy.cAngel Pons2020-03-261-614/+0
* nb/intel/sandybridge: Unify the code pathsAngel Pons2020-03-261-6/+18
* nb/intel/sandybridge: Add print for PLL_REF100_CFGAngel Pons2020-03-261-1/+3
* nb/intel/sandybridge: Rewrite get_FRQAngel Pons2020-03-261-14/+16
* nb/intel/sandybridge: Cache FRQ indexAngel Pons2020-03-251-17/+14
* nb/intel/sandybridge: Rewrite table accessorsAngel Pons2020-03-251-45/+48
* nb/intel/sandybridge: Factor out timing tablesAngel Pons2020-03-251-120/+37
* nb/intel/sandybridge: Use SPDX headersAngel Pons2020-03-251-13/+2
* nb/intel/sandybridge: Use cached CPUIDAngel Pons2020-03-231-1/+1
* nb/intel/sandybridge: Tidy up code and commentsAngel Pons2020-03-181-238/+179
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-3/+0
* nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons2020-01-101-27/+27
* nb/intel/sandybridge: Make MCHBAR arithmetics consistentAngel Pons2020-01-091-2/+2
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* src: Remove unneeded whitespaceElyes HAOUAS2018-10-231-1/+1
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-041-1/+0
* nb/intel/sandybridge: support more XMP timingsDan Elkouby2018-04-161-1/+4
* nb/intel/ivybridge: Improve CAS freq selectionArthur Heymans2017-06-121-99/+101
* nb/intel/sandybridge/raminit: Add default valuesPatrick Rudolph2017-04-041-3/+48
* nb/intel/sandybridge/raminit: Add 100MHz refclock supportPatrick Rudolph2017-04-041-3/+40
* nb/intel/sandybridge/raminit: Use Ivy Bridge specific valuesPatrick Rudolph2017-04-041-93/+248
* nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timingsArthur Heymans2017-03-271-10/+10
* nb/intel/sandybridge/raminit: Separate Sandybridge and IvybridgePatrick Rudolph2016-12-161-0/+514
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