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path: root/src/northbridge/intel/x4x/Makefile.inc
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* northbridge: Rename Makefiles from .inc to .mkMartin Roth2024-01-241-23/+0
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-151-0/+2
* nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-0/+1
* northbridge/intel: Rename ram_calc.c to memmap.cKyösti Mälkki2019-08-071-3/+3
* intel/i945,gm45,pineview,x4x: Move stage cache support functionKyösti Mälkki2019-08-031-3/+0
* nb/intel/x4x: Put stage cache in TSEGArthur Heymans2019-01-241-0/+3
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-051-0/+2
* nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans2018-05-141-1/+1
* nb/intel/x4x: Implement both read and write trainingArthur Heymans2018-05-011-0/+1
* nb/intel/x4x: Refactor setting default dll settingsArthur Heymans2018-04-171-0/+1
* nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans2017-08-201-0/+1
* nb/intel/x4x: Implement resume from S3 suspendArthur Heymans2017-02-171-1/+0
* nb/intel/x4x: Add DMI/EP initDamien Zammit2016-05-311-0/+1
* northbridge/intel/x4x: Native raminitDamien Zammit2015-12-301-0/+2
* northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit2015-12-291-0/+27
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