| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi | 2020-05-06 | 1 | -12/+1 |
| * | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi | 2020-05-06 | 1 | -2/+1 |
| * | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi | 2020-03-17 | 1 | -1/+0 |
| * | arch/io.h: Drop unnecessary include | Kyösti Mälkki | 2019-03-04 | 1 | -1/+0 |
| * | src: Fix typo | Elyes HAOUAS | 2018-08-10 | 1 | -1/+1 |
| * | nb/intel/x4x: Adapt post JEDEC for DDR3 | Arthur Heymans | 2018-05-24 | 1 | -0/+17 |
| * | nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings | Arthur Heymans | 2018-05-24 | 1 | -0/+81 |
| * | nb/intel/x4x: Add DDR3 JEDEC init | Arthur Heymans | 2018-05-24 | 1 | -0/+19 |
| * | nb/intel/x4x: Add a convenient macro to loop over bytelanes | Arthur Heymans | 2018-04-17 | 1 | -10/+10 |
| * | nb/intel/x4x: Refactor setting default dll settings | Arthur Heymans | 2018-04-17 | 1 | -0/+271 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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