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path: root/src/northbridge/intel/x4x/x4x.h
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* nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons2020-08-041-0/+2
* nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons2020-08-041-1/+1
* nb/intel/x4x: Put host bridge registers into its own fileAngel Pons2020-08-031-33/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh2020-04-281-1/+1
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-3/+0
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-151-1/+0
* nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-0/+3
* nb/intel/x4x.h: Include stdint.hArthur Heymans2019-11-131-0/+1
* nb/intel/x4x/x4x.h: Include iomap.hArthur Heymans2019-11-041-0/+2
* nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki2019-09-281-4/+2
* nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps}Elyes HAOUAS2019-06-211-2/+2
* nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans2018-12-031-0/+1
* northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held2018-07-301-0/+12
* nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans2018-06-141-0/+1
* nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans2018-05-241-0/+1
* nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans2018-05-241-0/+3
* nb/intel/x4x: Implement write levelingArthur Heymans2018-05-241-0/+2
* nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans2018-05-241-0/+2
* nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans2018-05-141-0/+1
* nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans2018-05-141-1/+1
* nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans2018-05-141-1/+0
* nb/intel/x4x: Implement both read and write trainingArthur Heymans2018-05-011-0/+6
* nb/x4x: Get rid of device_tElyes HAOUAS2018-04-301-1/+2
* nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans2018-04-171-17/+22
* nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans2018-04-171-0/+20
* nb/intel/x4x: Refactor setting default dll settingsArthur Heymans2018-04-171-16/+28
* nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans2018-04-171-2/+12
* nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans2017-12-161-21/+10
* nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans2017-08-201-0/+1
* nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans2017-05-221-0/+9
* nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans2017-03-211-14/+22
* nb/intel/x4x: Implement resume from S3 suspendArthur Heymans2017-02-171-1/+1
* nb/intel/x4x: Fix raminit on reset pathArthur Heymans2017-02-171-2/+5
* nb/x4x: Fix sticky scratchpad register offsetArthur Heymans2016-12-031-3/+1
* nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculationNico Huber2016-11-281-1/+2
* nb/intel/x4x: Fix and deflate `dimm_config` in raminitNico Huber2016-11-261-0/+4
* nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth2016-11-211-1/+1
* src/northbridge: Improve code formattingElyes HAOUAS2016-09-121-23/+23
* northbridge/intel/x4x: transition away from device_tAntonello Dettori2016-09-101-0/+2
* nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit2016-09-071-1/+1
* nb/intel/x4x: Fix unpopulated valueDamien Zammit2016-06-041-9/+10
* nb/intel/x4x: Add DMI/EP initDamien Zammit2016-05-311-0/+1
* nb/intel/x4x: Tidy up northbridgeDamien Zammit2016-01-291-1/+10
* northbridge/intel/x4x: clean up includesMartin Roth2016-01-131-4/+2
* northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit2015-12-291-0/+320
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