summaryrefslogtreecommitdiffstats
path: root/src/northbridge/intel
Commit message (Expand)AuthorAgeFilesLines
* nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans2018-06-072-2/+7
* nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans2018-06-071-0/+5
* nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans2018-06-073-45/+29
* intel/e7505: Remove ROMCC workaroundKyösti Mälkki2018-06-061-27/+3
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-068-9/+0
* arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-061-0/+1
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-052-0/+4
* cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+13
* nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese2018-06-041-4/+3
* intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki2018-06-042-5/+2
* src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-06-043-3/+3
* nb/intel: Use postcar_frame_add_romcache()Nico Huber2018-06-046-12/+6
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-0415-20/+0
* intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-023-7/+10
* intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-021-0/+1
* intel/e7505: Assume AGP slot disabledKyösti Mälkki2018-06-022-4/+21
* aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki2018-06-025-141/+133
* intel/e7505: Fix domain resourcesKyösti Mälkki2018-06-021-3/+9
* {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber2018-05-316-6/+6
* src/northbridge: Add and update license headersMartin Roth2018-05-2918-3/+235
* nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS2018-05-241-1/+1
* nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans2018-05-243-4/+33
* nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans2018-05-243-27/+136
* nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans2018-05-241-0/+8
* nb/intel/x4x: Implement write levelingArthur Heymans2018-05-243-2/+417
* nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans2018-05-244-7/+115
* nb/intel/sandybridge: Get rid of device_tElyes HAOUAS2018-05-241-1/+1
* nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari2018-05-211-1/+5
* nb/common/intel: Remove the mrc cache codeArthur Heymans2018-05-184-329/+0
* nb/intel/nehalem: Use the common mrc cache driverArthur Heymans2018-05-183-17/+10
* nb/intel/e7505: Get rid of device_tElyes HAOUAS2018-05-181-4/+5
* nb/intel/haswell: Get rid of device_tElyes HAOUAS2018-05-185-22/+27
* nb/intel/nehalem: Add ACPI pathPatrick Rudolph2018-05-171-0/+21
* nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS2018-05-143-12/+14
* nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS2018-05-141-4/+2
* nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans2018-05-141-5/+37
* nb/intel/x4x: Add DDR3 rcompArthur Heymans2018-05-141-31/+94
* nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans2018-05-141-56/+168
* nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans2018-05-141-37/+76
* nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans2018-05-142-9/+79
* nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans2018-05-141-6/+16
* nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans2018-05-144-40/+30
* nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans2018-05-142-27/+208
* nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans2018-05-141-27/+59
* nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS2018-05-111-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 09:16:12 +0000