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* nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans2018-06-072-2/+7
| | | | | | | | | | TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans2018-06-071-0/+5
| | | | | | | | | | | | TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans2018-06-073-45/+29
| | | | | | | | | | | | | This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/e7505: Remove ROMCC workaroundKyösti Mälkki2018-06-061-27/+3
| | | | | | | | | | Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-068-9/+0
| | | | | | | | | | | | | No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-061-0/+1
| | | | | | | | | | | To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-052-0/+4
| | | | | | | | | | | Tested on Google Peppy (Acer C720). Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26793 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
| | | | | | | | | | | | Also removes some non-POSTCAR_STAGE functions, since those are unused now. Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26792 Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+13
| | | | | | | | | | Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
| | | | | | | | Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
| | | | | | | | Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
| | | | | | | | Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
| | | | | | | | Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese2018-06-041-4/+3
| | | | | | | | | | | | | | | | | | | | * Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki2018-06-042-5/+2
| | | | | | | | Change-Id: I08c28862cc66956bdcab6ac9362b3d50bb64e78f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-06-043-3/+3
| | | | | | | | Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* nb/intel: Use postcar_frame_add_romcache()Nico Huber2018-06-046-12/+6
| | | | | | | | Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-0415-20/+0
| | | | | | | | Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-023-7/+10
| | | | | | | | | Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-021-0/+1
| | | | | | | | Change-Id: Icc4cef468ede2c1db052850efd155b626e392dae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26744 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/e7505: Assume AGP slot disabledKyösti Mälkki2018-06-022-4/+21
| | | | | | | | | | | | | | | Reducing two AGP aperture windows from default 256 MiB to chipset minimum 4 MiB releases 504 MiB of unused MMIO space. Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB. Supported CPUs are 32-bit with PAE, so there is a little reason to avoid overlarge MMIO region. Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki2018-06-025-141/+133
| | | | | | | | | | | | | | | | With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* intel/e7505: Fix domain resourcesKyösti Mälkki2018-06-021-3/+9
| | | | | | | | | | | | Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber2018-05-316-6/+6
| | | | | | | | | Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* src/northbridge: Add and update license headersMartin Roth2018-05-2918-3/+235
| | | | | | | | | | | | This change adds and updates headers in all of the northbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all northbridge directories. Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS2018-05-241-1/+1
| | | | | | | | | | | Missing '*const' in Change #26195 added into function northbridge_get_tseg_base(void). Change-Id: Ideb9a9cb98d34f2ed1034b8ee20b3b06aa5ff1e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26455 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans2018-05-243-4/+33
| | | | | | | | Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans2018-05-243-27/+136
| | | | | | | | Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans2018-05-241-0/+8
| | | | | | | | | | | | | When programming the final dram attribute and dram boundary settings, on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM Refresh Control) register as documented in "Intel ® 4 Series Chipset Family" documentation. Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/x4x: Implement write levelingArthur Heymans2018-05-243-2/+417
| | | | | | | | | | | | | | DDR3 adapted a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. After that the DQS signal gets sampled over DQ until a transition from high to low is found. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans2018-05-244-7/+115
| | | | | | | | | | | | | | | | Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs) This also modifies the send_jedec_cmd function as DDR3 dimms can have ranks mirrored which needs to be accounted for. The ddr3_emrs1_config array is placed externally since it is also needed for write leveling. Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/sandybridge: Get rid of device_tElyes HAOUAS2018-05-241-1/+1
| | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: If36a879fbe7a93a214d74dbfa6fb3ee2d09a044a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari2018-05-211-1/+5
| | | | | | | | | | | | | | | | | | Stack smashing was detected during raminit when not loading from MRC. Adding CAR_GLOBAL to a struct inside raminit was suggested in https://mail.coreboot.org/pipermail/coreboot/2018-May/086677.html in order to fix the problem. Adding CAR_GLOBAL to the ram timings variable solves the issue (adding it to the ram_training or raminfo struct had no effect). This is just a workaround and might need a proper fix in the future. Tested on Lenovo X201i with 2+2 and 4+4 GB RAM. Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1 Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/26388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/common/intel: Remove the mrc cache codeArthur Heymans2018-05-184-329/+0
| | | | | | | | | | | | This is now unused, since all intel northbridges now use the equivalent in drivers/mrc_cache. Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23485 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/nehalem: Use the common mrc cache driverArthur Heymans2018-05-183-17/+10
| | | | | | | | | | | | The common mrc cache driver allows to save the raminit training results to a separate fmap region which is more manageable than a cbfsfile. Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/e7505: Get rid of device_tElyes HAOUAS2018-05-181-4/+5
| | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: I2176ea83fac30052c02d9f6e98c89c40436a38e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/haswell: Get rid of device_tElyes HAOUAS2018-05-185-22/+27
| | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: I10fb736a7406a6571dffce883fb82c2711526762 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/nehalem: Add ACPI pathPatrick Rudolph2018-05-171-0/+21
| | | | | | | | | | | | | Provide a valid ACPI path for coreboot's SSDT generators. Fixes all ACPI errors found while booting GNU Linux 4.15 on Lenovo T410. Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/26287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS2018-05-143-12/+14
| | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS2018-05-141-4/+2
| | | | | | | | | | | Braces {} are not necessary for single statement blocks. Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans2018-05-141-5/+37
| | | | | | | | Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19876 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Add DDR3 rcompArthur Heymans2018-05-141-31/+94
| | | | | | | | Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19875 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans2018-05-141-56/+168
| | | | | | | | | | Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans2018-05-141-37/+76
| | | | | | | | | | | Also throws in some minor fixes like the wrong conditional for bankmod and using real CAS when programming MCHBAR(0x248). Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans2018-05-142-9/+79
| | | | | | | | | | Adds nmode to the sysinfo struct as it is needed later on. Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19872 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans2018-05-141-6/+16
| | | | | | | | | | | A few values were wrong, but it does not seem to matter all that much. Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19871 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans2018-05-144-40/+30
| | | | | | | | | | | | This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans2018-05-142-27/+208
| | | | | | | | | | | Since this memory controller supports both DDR2 and DDR3 allow it to decode both while making the dram type mutually exclusive. Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans2018-05-141-27/+59
| | | | | | | | | | | | | | | | | | | | | | | Some things in programming registers related to dual channel interleaved operation were wrong. This also adds some code that could in the future be used when me is active and claims some memory for its UMA. This also uses some more sensible variable names to clarify at least some of the magic. This fixes memtest86+ failing with some assymetric DIMM configuration. TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM configuration setups (would instantly fail at addresses above 4G on many configurations). Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS2018-05-111-2/+2
| | | | | | | | Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 02:34:31 +0000