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* src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS2020-09-021-1/+0
* {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS2020-09-021-1/+1
* nb/intel/sandybridge: Add ECC error injection register informationAngel Pons2020-08-311-0/+82
* mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen2020-08-245-30/+32
* nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon2020-08-243-3/+3
* src: Remove unused 'include <delay.h>'Elyes HAOUAS2020-08-181-1/+0
* nb/amd/agesa: read 256 bytes to SPD buffer instead of 128Mike Banon2020-08-173-3/+3
* src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS2020-08-171-3/+4
* nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS2020-08-171-3/+0
* nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons2020-08-121-18/+18
* nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph2020-08-111-2/+8
* nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph2020-08-111-85/+114
* nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph2020-08-112-3/+31
* nb/intel/sandybridge: Drop inexistent device from DMARAngel Pons2020-08-061-2/+0
* nb/intel/sandybridge: Deduplicate PCIEXBAR decodingAngel Pons2020-08-063-34/+7
* nb/intel/sandybridge: Refactor `get_pcie_bar`Angel Pons2020-08-061-16/+17
* {nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik2020-08-051-6/+2
* src: Use space after 'if', 'for'Elyes HAOUAS2020-08-052-2/+2
* src: Use space after switch, whileElyes HAOUAS2020-08-051-2/+2
* nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons2020-08-046-52/+52
* nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-16/+22
* nb/intel/x4x: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons2020-08-041-28/+28
* nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+7
* nb/intel/i945: Refactor `get_pcie_bar`Angel Pons2020-08-041-19/+20
* nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons2020-08-041-3/+3
* nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons2020-08-041-34/+32
* nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons2020-08-041-4/+4
* nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-35/+11
* nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/pineview: Use `MiB` definitionAngel Pons2020-08-043-9/+10
* nb/intel/pineview: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+6
* nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons2020-08-041-3/+4
* nb/intel/gm45: Use PCI bitwise opsAngel Pons2020-08-048-140/+74
* nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui2020-08-041-0/+1
* nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons2020-08-033-4/+8
* nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons2020-08-033-4/+9
* nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons2020-08-032-13/+23
* nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons2020-08-032-13/+18
* nb/intel/ironlake: Add QPI Link register definitionsAngel Pons2020-08-032-5/+10
* nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons2020-08-032-5/+10
* nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons2020-08-032-4/+7
* nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons2020-08-034-4/+5
* nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons2020-08-036-17/+20
* nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons2020-08-034-33/+33
* nb/intel/ironlake: Rename memory map variablesAngel Pons2020-08-032-26/+26
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