summaryrefslogtreecommitdiffstats
path: root/src/northbridge
Commit message (Expand)AuthorAgeFilesLines
...
* nb/intel/ironlake/raminit.c: Drop unused defineAngel Pons2020-08-031-2/+0
* nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASEAngel Pons2020-08-031-2/+0
* nb/intel/ironlake/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-32/+21
* nb/intel/ironlake: Put host bridge registers into its own fileAngel Pons2020-08-032-39/+50
* nb/intel/pineview/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-3/+4
* nb/intel/pineview: Put host bridge registers into its own fileAngel Pons2020-08-032-49/+57
* nb/intel/x4x/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-23/+23
* nb/intel/x4x: Put host bridge registers into its own fileAngel Pons2020-08-032-33/+41
* nb/intel/haswell: Add Crystal Well PCI IDsIru Cai2020-08-034-3/+15
* nb/intel/haswell: Configure VCs on Egress PortAngel Pons2020-07-311-0/+17
* nb/intel/x4x/rcven.c: Rename memory barrier functionAngel Pons2020-07-301-3/+3
* nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph2020-07-304-3/+112
* nb/intel/i945/gma.c: Remove extra indentationElyes HAOUAS2020-07-281-5/+4
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-282-0/+52
* nb/amd/pi/00730F01/northbridge.c: Add include <types.h>Elyes HAOUAS2020-07-261-1/+1
* src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth2020-07-264-8/+8
* nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS2020-07-261-1/+1
* nb/intel/sandybridge: Add missing includesElyes HAOUAS2020-07-2611-2/+18
* nb/intel/ironlake/raminit.c: initialize 'reply.command'Elyes HAOUAS2020-07-251-0/+4
* nb/intel/haswell/hostbridge_regs.h: Clean up registersAngel Pons2020-07-251-6/+13
* nb/intel/sandybridge: Put host bridge registers into its own fileAngel Pons2020-07-242-51/+59
* nb/intel/haswell: Put host bridge registers into its own fileAngel Pons2020-07-242-60/+69
* nb/intel/sandybridge: Remove unnecessary `struct sys_info`Angel Pons2020-07-242-8/+0
* nb/intel/ironlake: Move southbridge code to ibexpeakAngel Pons2020-07-241-19/+1
* nb/intel/i945: Put names to northbridge PCI devicesAngel Pons2020-07-225-55/+61
* sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons2020-07-202-2/+2
* src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS2020-07-142-2/+0
* src: Remove unused 'include <stdint.h>Elyes HAOUAS2020-07-141-1/+0
* src: Remove unused 'include <types.h>'Elyes HAOUAS2020-07-142-2/+0
* nb/intel/haswell/romstage.c: Align pei_data initializersAngel Pons2020-07-121-19/+19
* haswell: Move some MRC settings to devicetreeAngel Pons2020-07-122-0/+12
* haswell: Automatically check if Intel GbE is to be enabledAngel Pons2020-07-121-0/+4
* haswell: Add function to retrieve SPD addressesAngel Pons2020-07-122-0/+7
* haswell: Automatically determine system typeAngel Pons2020-07-121-0/+1
* haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons2020-07-122-0/+9
* haswell: Factor out `max_ddr3_freq`Angel Pons2020-07-121-0/+1
* haswell: Compute disabled channel masks at runtimeAngel Pons2020-07-121-0/+15
* mb/asrock/b85m_pro4: Factor out common MRC settingsAngel Pons2020-07-121-0/+12
* haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons2020-07-123-8/+16
* haswell: Drop `struct romstage_params` typeAngel Pons2020-07-122-10/+7
* haswell: Make `copy_spd` a weak functionAngel Pons2020-07-123-3/+9
* nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons2020-07-112-0/+7
* arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki2020-07-116-8/+7
* nb/intel/i945: Drop dead codeAngel Pons2020-07-112-45/+1
* nb/amd/agesa/agesa_helper.h: Drop dead codeAngel Pons2020-07-101-5/+0
* nb/intel/gm45/acpi/gm45.asl: Drop dead codeAngel Pons2020-07-091-28/+0
* nb/intel/ironlake/raminit.c: Drop dead codeAngel Pons2020-07-091-23/+0
* haswell: Drop GPIO indirection layersAngel Pons2020-07-092-2/+1
* haswell: Turn RCBA configuration into a functionAngel Pons2020-07-092-3/+1
* haswell: relocate `romstage_common` to northbridgeAngel Pons2020-07-083-0/+92
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 18:27:42 +0000