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* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-10-1818-128/+78
* nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans2018-10-151-0/+1
* nb/intel/x4x: Program read training results to all ranksArthur Heymans2018-10-151-3/+9
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-4/+4
* src: Replace MSR addresses with macrosElyes HAOUAS2018-10-111-2/+2
* selfboot: remove bounce buffersRonald G. Minnich2018-10-111-4/+0
* Move compiler.h to commonlibNico Huber2018-10-0812-15/+0
* src: Use tabs for indentationElyes HAOUAS2018-10-083-3/+3
* nb/intel/{gm45,i945,pineview}: Use macro instead of GGC addressElyes HAOUAS2018-10-083-3/+3
* src/*: normalize Google copyright headersPatrick Georgi2018-09-282-2/+1
* northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS2018-09-2517-23/+30
* nb/via/vx900: Get rid of device_tElyes HAOUAS2018-09-211-4/+4
* nb/amd/pi/00730F01: use MMIO and performance counters from AGESAPiotr Król2018-09-201-23/+38
* nb/amd/pi/00730F01: Don't use device_t in ramstageElyes HAOUAS2018-09-181-1/+1
* nb/intel/x4x: Don't use cached settings if CPU FSB has been changedArthur Heymans2018-09-161-1/+8
* nb/amd/pi/00730F01: Add initial native IVRS supportTimothy Pearson2018-09-151-12/+212
* nb/amd/pi/00730F01: Initialize IOMMU deviceKyösti Mälkki2018-09-153-1/+63
* nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resumeNico Huber2018-09-141-1/+2
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-141-1/+2
* complier.h: add __noreturn and use it in code baseAaron Durbin2018-09-101-1/+2
* nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner2018-09-051-1/+1
* nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans2018-08-226-37/+81
* nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph2018-08-211-61/+5
* nb/intel/pineview: Use a common MMCONF_BASE_ADDRESSArthur Heymans2018-08-211-0/+4
* nb/intel/pineview: Use the correct address for the RCVEN strobeArthur Heymans2018-08-211-1/+3
* nb/intel/pineview: Use i2c block read to fetch SPDArthur Heymans2018-08-211-12/+5
* nb/intel/raminit: Remove unused headersPatrick Rudolph2018-08-201-4/+0
* nb/intel/sandybridge/raminit: Fix DIMM type mappingPatrick Rudolph2018-08-201-1/+23
* nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph2018-08-201-0/+4
* sandybridge/raminit_common.c: fix printram statementIru Cai2018-08-171-5/+8
* Fix PCI ACPI _OSC methodsMarc Jones2018-08-171-5/+1
* nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap regionArthur Heymans2018-08-131-3/+11
* src: Fix typoElyes HAOUAS2018-08-1010-15/+15
* src/northbridge: Fix typoElyes HAOUAS2018-08-0910-14/+14
* cpu/amd: Correct number of MCA banks clearedMarshall Dawson2018-08-081-0/+1
* x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held2018-08-041-144/+99
* nehalem/raminit: remove read_mchbar functionsFelix Held2018-08-041-70/+39
* nehalem/raminit: clean up code and remove write_mchbar functionsFelix Held2018-08-041-45/+28
* northbridge/nehalem: add MCHBAR8/16 AND_OR macrosFelix Held2018-08-041-0/+4
* nehalem/raminit: clean up code and use MCHBAR macrosFelix Held2018-08-041-759/+690
* nehalem/raminit: remove REAL define and most dead codeFelix Held2018-08-041-95/+6
* sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier2018-08-031-2/+0
* sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held2018-08-011-41/+21
* sandybridge/raminit_common: use macro for execute command queue registerFelix Held2018-08-011-34/+79
* sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held2018-08-011-6/+8
* sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held2018-08-011-9/+8
* sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held2018-08-011-39/+26
* northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held2018-08-011-1/+4
* nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans2018-08-011-7/+11
* nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans2018-08-011-7/+9
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