summaryrefslogtreecommitdiffstats
path: root/src/northbridge
Commit message (Expand)AuthorAgeFilesLines
...
* nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans2018-08-011-5/+7
* nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans2018-08-011-9/+11
* x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held2018-07-301-222/+224
* nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans2018-07-307-7/+60
* northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held2018-07-301-0/+12
* northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held2018-07-301-1/+8
* northbridge/nehalem: clean up header fileFelix Held2018-07-301-38/+11
* sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held2018-07-291-666/+546
* sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held2018-07-291-3/+3
* sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held2018-07-291-9/+9
* nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph2018-07-291-1/+1
* nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph2018-07-284-95/+0
* nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph2018-07-281-39/+0
* intel/sandybridge: Don't hardcode platform typePatrick Rudolph2018-07-288-16/+58
* nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph2018-07-261-1/+1
* nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph2018-07-262-3/+11
* nb/intel/nehalem: Remove the C native graphic initArthur Heymans2018-07-262-461/+4
* drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese2018-07-251-4/+0
* nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph2018-07-251-1/+1
* nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph2018-07-251-10/+12
* AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki2018-07-235-325/+24
* AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki2018-07-207-104/+9
* nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS2018-07-121-30/+37
* src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-0914-56/+57
* src/nb: Fix non-local header treated as localElyes HAOUAS2018-07-027-7/+7
* arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier2018-06-303-14/+14
* sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans2018-06-296-10/+51
* sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans2018-06-292-3/+17
* nb/intel/i945: Remove dead codeElyes HAOUAS2018-06-231-7/+0
* Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans2018-06-215-5/+0
* nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki2018-06-201-3/+6
* nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-173-7/+8
* nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-171-1/+0
* cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki2018-06-171-0/+34
* nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph2018-06-172-5/+5
* nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans2018-06-171-0/+5
* cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans2018-06-141-7/+0
* nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS2018-06-141-1/+1
* nb/intel/x4x: Deprecate native graphic initArthur Heymans2018-06-142-339/+1
* nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans2018-06-141-10/+44
* nb/intel/x4x: Work around a quirkArthur Heymans2018-06-141-0/+21
* nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans2018-06-142-13/+36
* src: Get rid of unneeded whitespaceElyes HAOUAS2018-06-1420-42/+44
* src: Get rid of device_tElyes HAOUAS2018-06-141-16/+27
* src: Use of device_t is deprecatedElyes HAOUAS2018-06-149-36/+36
* AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki2018-06-142-12/+0
* {src,util}: Use NULL instead of 0 for pointerElyes HAOUAS2018-06-111-2/+2
* libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber2018-06-082-1/+10
* nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans2018-06-072-2/+7
* nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans2018-06-071-0/+5
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 12:58:50 +0000