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* sb/amd/pi/hudson: remove unused Bolton PI FCH codeFelix Held2021-04-111-1/+0
* spd.h: Move `DIMMx` macros to i440bx/raminit.hAngel Pons2021-04-111-0/+6
* nb/intel/i945: Use new fixed BAR accessorsAngel Pons2021-04-105-381/+380
* nb/intel/gm45: Use new fixed BAR accessorsAngel Pons2021-04-1012-609/+598
* nb/intel/gm45/gm45.h: Guard `CxDRC1_NOTPOP` macro parametersAngel Pons2021-04-101-1/+1
* nb/intel/x4x: Use new fixed BAR accessorsAngel Pons2021-04-106-500/+484
* nb/intel/x4x: Correct and use macros for CLKCFGAngel Pons2021-04-104-6/+7
* nb/intel/x4x/dq_dqs.c: Avoid breaking strings over multiple linesAngel Pons2021-04-101-17/+11
* nb/intel/x4x: Add missing newlines to log messageAngel Pons2021-04-101-2/+2
* nb/intel/x4x: Reflow long linesAngel Pons2021-04-106-254/+133
* nb/intel/x4x/dq_dqs.c: Fix typo in variable nameAngel Pons2021-04-101-3/+3
* nb/intel/x4x: Correct sync DLL phase searchAngel Pons2021-04-101-1/+1
* nb/intel/pineview: Replace remaining BAR accessorsAngel Pons2021-04-101-12/+10
* nb/intel/pineview: Use new fixed BAR accessorsAngel Pons2021-04-103-477/+478
* nb/intel/ironlake: Use new fixed BAR accessorsAngel Pons2021-04-104-660/+646
* nb/intel: Replace remaining BAR accessorsAngel Pons2021-04-102-24/+5
* nb/intel/sandybridge: Use new fixed BAR accessorsAngel Pons2021-04-1012-336/+320
* nb/intel/haswell: Use new fixed BAR accessorsAngel Pons2021-04-104-98/+70
* nb/intel/common/fixed_bars.h: Add new read/write accessorsAngel Pons2021-04-101-0/+66
* nb/intel: Factor out remaining MCHBAR macrosAngel Pons2021-04-106-49/+10
* nb/intel/i440bx: Enable bootblock consoleKeith Hui2021-04-061-1/+0
* arch/x86: Provide readXp/writeXp helpers in arch/mmio.hAngel Pons2021-04-061-10/+0
* nb/intel/haswell: Ensure MCH has acked raminitAngel Pons2021-04-061-0/+10
* nb/intel/sandybridge: Drop `pci_mmio_size`Angel Pons2021-04-052-24/+3
* nb/intel/ironlake: Drop `pci_mmio_size`Angel Pons2021-04-052-23/+1
* nb/intel/sandybridge: Rename `pdwm_mode` enumAngel Pons2021-04-052-3/+3
* nb/intel/i945/raminit.c: Replace `DIMM0`Angel Pons2021-04-051-1/+1
* nb/intel/i945: Refactor `dump_spd_registers` functionAngel Pons2021-04-053-9/+10
* device/dram/ddr3: Get rid of useless typedefsAngel Pons2021-04-054-5/+5
* nb/intel/pineview: Correct COMP register writeAngel Pons2021-04-021-2/+2
* nb/intel/pineview/raminit.c: Correct clkset1 programmingAngel Pons2021-03-281-2/+1
* nb/intel/pineview: Correct HICLKGTCTL writeAngel Pons2021-03-281-1/+1
* nb/intel/pineview: Drop MCHBAR macro from DMIBAR accessAngel Pons2021-03-281-1/+1
* nb/intel/ironlake/quickpath.c: Correct one valueAngel Pons2021-03-281-1/+1
* nb/intel/ironlake: Drop copy-pasted finalisation stepsAngel Pons2021-03-281-15/+0
* nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`Angel Pons2021-03-282-8/+8
* nb/intel/haswell: Move USB config API into Lynx PointAngel Pons2021-03-251-42/+0
* nb/intel/haswell: Decouple mainboard USB config from MRCAngel Pons2021-03-253-19/+85
* nb/intel/haswell: Limit mainboard USB config array lengthsAngel Pons2021-03-232-4/+10
* nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons2021-03-232-3/+6
* nb/intel/haswell: Confine `pei_data` uses to raminit.cAngel Pons2021-03-233-133/+127
* nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons2021-03-192-7/+43
* mb/google/slippy: Correct memory-down SPD handlingAngel Pons2021-03-191-4/+5
* sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons2021-03-151-12/+7
* sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons2021-03-151-1/+1
* nb/intel/haswell: Finalize northbridge in ramstageAngel Pons2021-03-104-40/+33
* nb/intel/haswell/pcie.c: Add missing pre-ASPM initAngel Pons2021-03-103-0/+125
* nb/intel/haswell: Indent PCI ops with tabsAngel Pons2021-03-071-5/+5
* nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons2021-03-011-27/+11
* nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak2021-03-011-2/+2
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