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* AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki2018-07-235-325/+24
* AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki2018-07-207-104/+9
* nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS2018-07-121-30/+37
* src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-0914-56/+57
* src/nb: Fix non-local header treated as localElyes HAOUAS2018-07-027-7/+7
* arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier2018-06-303-14/+14
* sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans2018-06-296-10/+51
* sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans2018-06-292-3/+17
* nb/intel/i945: Remove dead codeElyes HAOUAS2018-06-231-7/+0
* Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans2018-06-215-5/+0
* nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki2018-06-201-3/+6
* nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-173-7/+8
* nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-171-1/+0
* cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki2018-06-171-0/+34
* nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph2018-06-172-5/+5
* nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans2018-06-171-0/+5
* cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans2018-06-141-7/+0
* nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS2018-06-141-1/+1
* nb/intel/x4x: Deprecate native graphic initArthur Heymans2018-06-142-339/+1
* nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans2018-06-141-10/+44
* nb/intel/x4x: Work around a quirkArthur Heymans2018-06-141-0/+21
* nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans2018-06-142-13/+36
* src: Get rid of unneeded whitespaceElyes HAOUAS2018-06-1420-42/+44
* src: Get rid of device_tElyes HAOUAS2018-06-141-16/+27
* src: Use of device_t is deprecatedElyes HAOUAS2018-06-149-36/+36
* AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki2018-06-142-12/+0
* {src,util}: Use NULL instead of 0 for pointerElyes HAOUAS2018-06-111-2/+2
* libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber2018-06-082-1/+10
* nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans2018-06-072-2/+7
* nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans2018-06-071-0/+5
* nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans2018-06-073-45/+29
* intel/e7505: Remove ROMCC workaroundKyösti Mälkki2018-06-061-27/+3
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-0610-11/+0
* arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki2018-06-064-0/+4
* northbridge/amd/lx: Fix function setShadowRCONFIru Cai2018-06-051-8/+8
* amd/geode_lx: Fix .c includesKyösti Mälkki2018-06-053-3/+9
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-052-0/+4
* cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+13
* nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese2018-06-041-4/+3
* intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki2018-06-042-5/+2
* src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-06-046-25/+27
* nb/intel: Use postcar_frame_add_romcache()Nico Huber2018-06-046-12/+6
* nb/via/vx900: Get rid of device_tElyes HAOUAS2018-06-046-47/+47
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-0415-20/+0
* intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-023-7/+10
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