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* nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons2020-03-205-97/+70
* nb/intel/sandybridge: Always write to PEGCTLAngel Pons2020-03-201-2/+3
* nb/intel/sandybridge: Use loops on DMI register groupsAngel Pons2020-03-191-137/+142
* nb/intel/sandybridge: Tidy up code and commentsAngel Pons2020-03-1822-1996/+2027
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-17206-282/+0
* nb/intel/i945/raminit: Simplify if conditionPaul Menzel2020-03-161-2/+2
* nb/intel/pineview: Clean up code and commentsAngel Pons2020-03-1511-1155/+1813
* treewide: Replace uses of "Nehalem"Angel Pons2020-03-151-3/+3
* nb/intel/nehalem: Rename to ironlakeAngel Pons2020-03-1519-42/+42
* nb/intel/i945/raminit: Use boolean type for helper variablesPaul Menzel2020-03-151-1/+1
* nb/intel/i945/raminit: Remove space for correct alignmentPaul Menzel2020-03-151-1/+1
* nb/intel/haswell: Tidy up code and commentsAngel Pons2020-03-1513-408/+430
* intel/i945: Call fixup_i945_errata() only for mobile versionElyes HAOUAS2020-03-113-3/+4
* src/nb: Use 'print("%s...", __func__)'Elyes HAOUAS2020-03-075-17/+15
* northbridge: Remove unused include <device/pci.h>Elyes HAOUAS2020-03-0613-13/+0
* nb/intel/haswell/peg: Add PEG driver stubChris Morgan2020-03-065-1/+152
* nb/intel/nehalem: Use cache.h functionsArthur Heymans2020-03-041-13/+8
* nb/amd/agesa/family14/acpi: Fix commentElyes HAOUAS2020-03-041-1/+1
* nb/intel/sandybridge: Fix VBOOTPatrick Rudolph2020-03-021-1/+25
* treewide: Capitalize 'CMOS'Elyes HAOUAS2020-02-244-6/+6
* src: capitalize 'RAM'Elyes HAOUAS2020-02-246-11/+11
* nb/intel/snb: Add PCI routing table for PEG root portsJames Ye2020-02-211-0/+20
* nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI IDJonathan A. Kollasch2020-02-181-1/+1
* nb/intel/sandybridge: use list of northbridge device IDsJonathan A. Kollasch2020-02-181-23/+5
* nb/amd/pi/00730F01: enable ACS and AER for PCIe portsMichał Żygowski2020-02-171-0/+31
* nb/intel/gm45: Fix typo in console messageElyes HAOUAS2020-02-171-1/+1
* nb/intel/nehalem: Remove unused MRC_CACHE_SIZEElyes HAOUAS2020-02-171-4/+0
* nb/intel/sandybridge/acpi: Fix MMCONF size computationPatrick Rudolph2020-02-121-1/+1
* nb/intel/sandybridge/acpi: Update PEG codePatrick Rudolph2020-02-121-8/+4
* nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)Chris Morgan2020-02-061-3/+3
* nb/intel/sandybridge: improve indexed register helper macrosFelix Held2020-02-011-5/+5
* amd/pi/00660F01: Add missing domain_acpi_name functionJorge Fernandez2020-01-301-0/+9
* nb/intel/i945: Use boot path macrosPaul Menzel2020-01-291-1/+1
* nb/intel/sandybridge/raminit_common.h: add missing stdint.h includeFelix Held2020-01-271-0/+2
* nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE defineFelix Held2020-01-272-4/+4
* intel/i440bx: Resolve long standing raminit TODOsKeith Hui2020-01-261-12/+2
* intel/i440bx: Add timestamp to RAM initKeith Hui2020-01-261-0/+3
* intel/i440bx: Use smbus_read_byte() for raminit debugKeith Hui2020-01-261-1/+2
* nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held2020-01-161-1/+1
* nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held2020-01-162-14/+19
* nb/intel/sandybridge: refactor code around lane_base[]Felix Held2020-01-161-10/+13
* nb/intel/sandybridge: refactor lane_registers[]Felix Held2020-01-152-17/+23
* nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held2020-01-151-8/+5
* nb/intel/sandybridge: Repurpose HOST_BRIDGE macroAngel Pons2020-01-151-34/+34
* intel/nehalem,ibexpeak: Move enable_smbus() callKyösti Mälkki2020-01-141-3/+0
* intel/sandybridge,bd82x6x: Move enable_smbus() callKyösti Mälkki2020-01-141-3/+0
* intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() callKyösti Mälkki2020-01-142-5/+0
* intel/{i945,pineview},i82801gx: Move enable_smbus() callKyösti Mälkki2020-01-142-5/+0
* nb/intel/sandybridge: Drop 'or zero' instancesAngel Pons2020-01-141-9/+6
* intel/e7505: Always enable DIMM compatibility checksKyösti Mälkki2020-01-121-16/+2
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