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northbridge
Commit message (
Expand
)
Author
Age
Files
Lines
*
nb/intel/x4x: Define and use `HOST_BRIDGE` macro
Angel Pons
2020-08-04
6
-52
/
+52
*
nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs
Angel Pons
2020-08-04
1
-16
/
+22
*
nb/intel/x4x: Remove dead assignments
Angel Pons
2020-08-04
1
-2
/
+1
*
nb/intel/x4x: Refactor `decode_pcie_bar`
Angel Pons
2020-08-04
1
-9
/
+5
*
nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding
Angel Pons
2020-08-04
1
-28
/
+28
*
nb/intel/i945: Deduplicate PCIEXBAR decoding
Angel Pons
2020-08-04
3
-32
/
+7
*
nb/intel/i945: Refactor `get_pcie_bar`
Angel Pons
2020-08-04
1
-19
/
+20
*
nb/intel/haswell: Use ASL 2.0 syntax
Angel Pons
2020-08-04
1
-3
/
+3
*
nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax
Angel Pons
2020-08-04
1
-34
/
+32
*
nb/intel/sandybridge: Update to ASL 2.0 syntax
Angel Pons
2020-08-04
1
-4
/
+4
*
nb/intel/x4x: Change signature of `decode_pciebar`
Angel Pons
2020-08-04
4
-4
/
+4
*
nb/intel/haswell: Deduplicate PCIEXBAR decoding
Angel Pons
2020-08-04
3
-35
/
+11
*
nb/intel/pineview: Refactor `decode_pcie_bar`
Angel Pons
2020-08-04
1
-9
/
+5
*
nb/intel/pineview: Change signature of `decode_pciebar`
Angel Pons
2020-08-04
4
-4
/
+4
*
nb/intel/pineview: Use `MiB` definition
Angel Pons
2020-08-04
3
-9
/
+10
*
nb/intel/pineview: Remove dead assignments
Angel Pons
2020-08-04
1
-2
/
+1
*
nb/intel/gm45: Deduplicate PCIEXBAR decoding
Angel Pons
2020-08-04
3
-32
/
+6
*
nb/intel/gm45/northbridge.c: Use `MiB` definition
Angel Pons
2020-08-04
1
-3
/
+4
*
nb/intel/gm45: Use PCI bitwise ops
Angel Pons
2020-08-04
8
-140
/
+74
*
nb/intel/i440bx: Make ROM area unavailable for MMIO
Keith Hui
2020-08-04
1
-0
/
+1
*
nb/intel/ironlake: Add Generic Non-Core register definitions
Angel Pons
2020-08-03
3
-4
/
+8
*
nb/intel/ironlake: Add Generic Non-Core PCI device definition
Angel Pons
2020-08-03
3
-4
/
+9
*
nb/intel/ironlake: Add QPI Physical Layer registers
Angel Pons
2020-08-03
2
-13
/
+23
*
nb/intel/ironlake: Add QPI Physical Layer device definition
Angel Pons
2020-08-03
2
-13
/
+18
*
nb/intel/ironlake: Add QPI Link register definitions
Angel Pons
2020-08-03
2
-5
/
+10
*
nb/intel/ironlake: Add definition for QPI Link PCI device
Angel Pons
2020-08-03
2
-5
/
+10
*
nb/intel/ironlake: Add SAD DRAM register definitions
Angel Pons
2020-08-03
2
-4
/
+7
*
nb/intel/ironlake: Correct PCIEXBAR definition
Angel Pons
2020-08-03
4
-4
/
+5
*
nb/intel/ironlake: Add definition for SAD PCI device
Angel Pons
2020-08-03
6
-17
/
+20
*
nb/intel/ironlake: Drop `D0F0_` prefix from register names
Angel Pons
2020-08-03
4
-33
/
+33
*
nb/intel/ironlake: Rename memory map variables
Angel Pons
2020-08-03
2
-26
/
+26
*
nb/intel/ironlake/raminit.c: Drop unused define
Angel Pons
2020-08-03
1
-2
/
+0
*
nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASE
Angel Pons
2020-08-03
1
-2
/
+0
*
nb/intel/ironlake/hostbridge_regs.h: Clean up registers
Angel Pons
2020-08-03
1
-32
/
+21
*
nb/intel/ironlake: Put host bridge registers into its own file
Angel Pons
2020-08-03
2
-39
/
+50
*
nb/intel/pineview/hostbridge_regs.h: Clean up registers
Angel Pons
2020-08-03
1
-3
/
+4
*
nb/intel/pineview: Put host bridge registers into its own file
Angel Pons
2020-08-03
2
-49
/
+57
*
nb/intel/x4x/hostbridge_regs.h: Clean up registers
Angel Pons
2020-08-03
1
-23
/
+23
*
nb/intel/x4x: Put host bridge registers into its own file
Angel Pons
2020-08-03
2
-33
/
+41
*
nb/intel/haswell: Add Crystal Well PCI IDs
Iru Cai
2020-08-03
4
-3
/
+15
*
nb/intel/haswell: Configure VCs on Egress Port
Angel Pons
2020-07-31
1
-0
/
+17
*
nb/intel/x4x/rcven.c: Rename memory barrier function
Angel Pons
2020-07-30
1
-3
/
+3
*
nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW
Patrick Rudolph
2020-07-30
4
-3
/
+112
*
nb/intel/i945/gma.c: Remove extra indentation
Elyes HAOUAS
2020-07-28
1
-5
/
+4
*
nb/intel/haswell: Enable DMI ASPM
Angel Pons
2020-07-28
2
-0
/
+52
*
nb/amd/pi/00730F01/northbridge.c: Add include <types.h>
Elyes HAOUAS
2020-07-26
1
-1
/
+1
*
src: Change BOOL CONFIG_ to CONFIG() in comments & strings
Martin Roth
2020-07-26
4
-8
/
+8
*
nb/intel/haswell: Use macro for dimm->bus_width
Elyes HAOUAS
2020-07-26
1
-1
/
+1
*
nb/intel/sandybridge: Add missing includes
Elyes HAOUAS
2020-07-26
11
-2
/
+18
*
nb/intel/ironlake/raminit.c: initialize 'reply.command'
Elyes HAOUAS
2020-07-25
1
-0
/
+4
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