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* nb/intel/gm45: Guard macro parametersAngel Pons2021-01-101-39/+39
* nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parametersAngel Pons2021-01-101-1/+1
* cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons2021-01-101-0/+22
* nb/intel/sandybridge: Use consistent comment styleAngel Pons2021-01-061-6/+6
* nb/intel/sandybridge: Define and use `QCLK_PI` constantAngel Pons2021-01-062-36/+49
* nb/intel/haswell/memmap.h: Clean upAngel Pons2021-01-051-7/+3
* nb/intel/sandybridge: Replace memset with initializerAngel Pons2021-01-041-3/+1
* nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner2021-01-012-22/+14
* soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner2021-01-012-11/+11
* drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier2020-12-308-3/+20
* soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner2020-12-291-2/+2
* kconfig: remove non-existent sourceJack Rosenthal2020-12-281-1/+0
* cpu/intel/model_206ax: Add more CPU steppingsAngel Pons2020-12-251-0/+1
* nb/intel/sandybridge: Move steppings to CPU headerAngel Pons2020-12-254-24/+2
* nb/intel/sandybridge: Rewrite constant valuesAngel Pons2020-12-254-33/+33
* nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons2020-12-252-1/+19
* nb/intel/sandybridge: Refactor ODT stretch table codeAngel Pons2020-12-231-6/+5
* nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`Angel Pons2020-12-231-28/+25
* nb/intel/sandybridge: Always wait for IOSAV after starting itAngel Pons2020-12-233-10/+4
* nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`Angel Pons2020-12-233-47/+24
* nb/intel/sandybridge: Remove unnecessary commentsAngel Pons2020-12-231-29/+1
* nb/intel/sandybridge: Print delays in decimalAngel Pons2020-12-231-14/+14
* nb/intel/sandybridge: Add comment to TC_RWP writeAngel Pons2020-12-231-0/+4
* nb/intel/sandybridge: Use proper names to refer to training stepsAngel Pons2020-12-231-11/+11
* nb/intel/sandybridge: Add comments about I/O and RT latencyAngel Pons2020-12-231-0/+21
* nb/intel/sandybridge: Rename I/O data timingsAngel Pons2020-12-233-146/+147
* nb/intel/sandybridge: Use bitfields for I/O data timingsAngel Pons2020-12-232-17/+48
* nb/intel/sandybridge: Compute data timings independentlyAngel Pons2020-12-231-53/+11
* drivers: Replace set_vbe_mode_info_validPatrick Rudolph2020-12-171-1/+2
* nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons2020-12-141-0/+9
* nb/intel/ironlake: Remove unused constantAngel Pons2020-12-141-2/+0
* nb/intel/sandybridge: Clean up program_timingsAngel Pons2020-12-131-50/+67
* nb/intel/sandybridge: Clean up stepping logicAngel Pons2020-12-123-41/+41
* nb/intel/sandybridge: Fix blunder in MR2 shadow codeAngel Pons2020-12-121-7/+6
* nb/intel/ironlake: Introduce memmap.hAngel Pons2020-12-072-9/+18
* nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons2020-12-072-16/+11
* nb/intel/i945: Introduce memmap.hPatrick Georgi2020-12-072-10/+18
* cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner2020-12-031-9/+3
* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-021-1/+1
* cbfs: Enable CBFS mcache on most chipsetsJulius Werner2020-12-024-0/+4
* nb/amd: Deduplicate nb_common.hAngel Pons2020-11-258-17/+6
* device: Drop unused HyperTransport codeAngel Pons2020-11-257-5/+6
* nb/amd/agesa/family15tn: define macros for GNB and IOMMU devicesMike Banon2020-11-231-0/+10
* nb/amd/agesa/family15tn: define macro for internal HDMI audio controllerMike Banon2020-11-231-0/+4
* nb/amd/pi: Remove 00660F01 directory & filesMartin Roth2020-11-227-1187/+0
* cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth2020-11-221-3/+0
* nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons2020-11-222-7/+55
* nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons2020-11-223-26/+16
* nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons2020-11-223-27/+26
* nb/intel/sandybridge: Only use write Vref if supportedAngel Pons2020-11-222-0/+8
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