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* mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen2020-11-132-9/+8
* nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons2020-11-131-0/+2
* nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons2020-11-131-6/+6
* nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons2020-11-132-35/+35
* nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons2020-11-131-61/+0
* nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVENAngel Pons2020-11-131-3/+12
* haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons2020-11-131-7/+7
* nb/intel/pineview: Fix clearing memoryArthur Heymans2020-11-091-3/+3
* haswell: Add Intel TXT support in romstageAngel Pons2020-11-041-0/+18
* nb/intel/haswell: Place CTDP ASL code in a separate scopeAngel Pons2020-11-042-5/+6
* nb/intel/haswell/acpi: Align with BroadwellAngel Pons2020-11-043-239/+245
* {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons2020-10-313-7/+7
* src: Include <arch/io.h> when appropriateElyes HAOUAS2020-10-262-1/+1
* nb/intel/haswell/gma.c: Drop unused ChromeOS includeAngel Pons2020-10-251-4/+0
* nb/intel/haswell/gma.c: Drop unused `set_translation_table` functionAngel Pons2020-10-252-42/+0
* nb/intel/haswell/gma.c: Drop space after unary `!`Angel Pons2020-10-241-1/+1
* nb/intel/haswell/gma.c: Move log message to the right placeAngel Pons2020-10-241-3/+2
* nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel`Angel Pons2020-10-241-1/+1
* nb/intel/haswell/early_init.c: Remove invalid register writesAngel Pons2020-10-241-10/+0
* nb/intel/haswell/finalize.c: Align with BroadwellAngel Pons2020-10-241-3/+3
* nb/intel/haswell/finalize.c: Align MC locking with BroadwellAngel Pons2020-10-241-3/+3
* nb/intel/haswell/finalize.c: Lock down MC ARB registerAngel Pons2020-10-242-0/+2
* nb/intel/haswell/finalize.c: Lock PCU DDR PTMAngel Pons2020-10-242-0/+3
* nb/intel/haswell/finalize.c: Drop obsolete SA PM lockAngel Pons2020-10-241-1/+0
* nb/intel/haswell/finalize.c: Use PCI register namesAngel Pons2020-10-241-11/+11
* nb/intel/gm45: Clean up header handlingAngel Pons2020-10-244-10/+4
* nb/intel/gm45: Introduce memmap.hAngel Pons2020-10-242-8/+16
* nb/intel/gm45: Add more DMIBAR/EPBAR registersAngel Pons2020-10-243-43/+78
* nb/intel/ironlake: Add more host bridge PCI IDsAngel Pons2020-10-241-4/+28
* nb/intel/ironlake: Generalise northbridge chip nameAngel Pons2020-10-241-1/+1
* nb/intel/haswell: Generalise northbridge chip nameAngel Pons2020-10-241-1/+1
* nb/intel/haswell: Set up Root Complex topologyAngel Pons2020-10-243-0/+79
* nb/intel/haswell/raminit.c: Clean up local variablesAngel Pons2020-10-232-16/+13
* nb/intel/sandybridge: Correct designation of MRC versionAngel Pons2020-10-231-2/+2
* nb/intel/haswell: Correct designation of MRC versionAngel Pons2020-10-231-4/+4
* nb/intel/haswell: Drop ASM to call into MRCAngel Pons2020-10-231-5/+4
* nb/intel/haswell: Constify pointers to stringsAngel Pons2020-10-231-1/+1
* nb/intel/haswell: Make MAD_DIMM_* registers indexedAngel Pons2020-10-232-7/+5
* nb/intel/haswell: Drop unnecessary register readAngel Pons2020-10-231-2/+0
* nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC optionAngel Pons2020-10-222-6/+26
* intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons2020-10-171-3/+7
* nb/intel/haswell: Account for DPR region in memory mapAngel Pons2020-10-153-11/+62
* nb/intel/x4x: Place raminit definitions in raminit.hAngel Pons2020-10-148-245/+259
* nb/intel/x4x: Move register headers into a subfolderAngel Pons2020-10-142-4/+4
* nb/intel/x4x: Clean up DMIBAR/EPBAR definitionsAngel Pons2020-10-142-44/+92
* nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate filesAngel Pons2020-10-133-58/+74
* nb/intel/sandybridge: Improve cbmem_top_chipset calculationAngel Pons2020-10-131-11/+9
* nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntaxElyes HAOUAS2020-10-121-8/+8
* nb/intel/ironlake: Move register headers into a subfolderAngel Pons2020-10-102-4/+4
* nb/intel/ironlake: Clean up DMIBAR/EPBAR registersAngel Pons2020-10-103-22/+29
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