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* nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons2020-08-046-52/+52
* nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-16/+22
* nb/intel/x4x: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons2020-08-041-28/+28
* nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+7
* nb/intel/i945: Refactor `get_pcie_bar`Angel Pons2020-08-041-19/+20
* nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons2020-08-041-3/+3
* nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons2020-08-041-34/+32
* nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons2020-08-041-4/+4
* nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-35/+11
* nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/pineview: Use `MiB` definitionAngel Pons2020-08-043-9/+10
* nb/intel/pineview: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+6
* nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons2020-08-041-3/+4
* nb/intel/gm45: Use PCI bitwise opsAngel Pons2020-08-048-140/+74
* nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui2020-08-041-0/+1
* nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons2020-08-033-4/+8
* nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons2020-08-033-4/+9
* nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons2020-08-032-13/+23
* nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons2020-08-032-13/+18
* nb/intel/ironlake: Add QPI Link register definitionsAngel Pons2020-08-032-5/+10
* nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons2020-08-032-5/+10
* nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons2020-08-032-4/+7
* nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons2020-08-034-4/+5
* nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons2020-08-036-17/+20
* nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons2020-08-034-33/+33
* nb/intel/ironlake: Rename memory map variablesAngel Pons2020-08-032-26/+26
* nb/intel/ironlake/raminit.c: Drop unused defineAngel Pons2020-08-031-2/+0
* nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASEAngel Pons2020-08-031-2/+0
* nb/intel/ironlake/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-32/+21
* nb/intel/ironlake: Put host bridge registers into its own fileAngel Pons2020-08-032-39/+50
* nb/intel/pineview/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-3/+4
* nb/intel/pineview: Put host bridge registers into its own fileAngel Pons2020-08-032-49/+57
* nb/intel/x4x/hostbridge_regs.h: Clean up registersAngel Pons2020-08-031-23/+23
* nb/intel/x4x: Put host bridge registers into its own fileAngel Pons2020-08-032-33/+41
* nb/intel/haswell: Add Crystal Well PCI IDsIru Cai2020-08-034-3/+15
* nb/intel/haswell: Configure VCs on Egress PortAngel Pons2020-07-311-0/+17
* nb/intel/x4x/rcven.c: Rename memory barrier functionAngel Pons2020-07-301-3/+3
* nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph2020-07-304-3/+112
* nb/intel/i945/gma.c: Remove extra indentationElyes HAOUAS2020-07-281-5/+4
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-282-0/+52
* nb/amd/pi/00730F01/northbridge.c: Add include <types.h>Elyes HAOUAS2020-07-261-1/+1
* src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth2020-07-264-8/+8
* nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS2020-07-261-1/+1
* nb/intel/sandybridge: Add missing includesElyes HAOUAS2020-07-2611-2/+18
* nb/intel/ironlake/raminit.c: initialize 'reply.command'Elyes HAOUAS2020-07-251-0/+4
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