| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cpu/x86: Drop !CPU_INFO_V2 code | Arthur Heymans | 2022-11-07 | 1 | -2/+2 |
| * | x86_64 assembly: Don't touch %gs | Patrick Rudolph | 2021-12-06 | 1 | -0/+6 |
| * | security/intel: Use defines for segment registers | Patrick Rudolph | 2021-12-06 | 1 | -2/+3 |
| * | sec/intel/txt: Split MTRR setup ASM code into a macro | Angel Pons | 2020-10-22 | 1 | -64/+10 |
| * | security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] | Angel Pons | 2020-10-17 | 1 | -17/+86 |
| * | sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPE | Arthur Heymans | 2020-10-15 | 1 | -6/+2 |
| * | security/intel/txt: Fix variable MTRR handling | Angel Pons | 2020-08-07 | 1 | -48/+47 |
| * | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese | 2020-07-31 | 1 | -0/+319 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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