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* src/{drivers,security}: Remove unused <string.h>Elyes HAOUAS2021-02-161-1/+0
* security/intel/txt/Makefile.inc: Use tab for indentElyes HAOUAS2021-02-111-4/+4
* drivers/security/cbnt: Fix bootblock sizeArthur Heymans2021-02-011-0/+2
* soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons2021-01-301-1/+1
* security/intel/stm/StmPlatformSmm.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi2021-01-152-4/+4
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-142-12/+4
* */Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans2021-01-082-0/+4
* security/intel/txt: Don't run SCHECK on CBnTArthur Heymans2021-01-071-1/+1
* security/intel/txt/ramstage.c: Fix clearing secrets on CBNTArthur Heymans2021-01-041-16/+14
* sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurableArthur Heymans2020-12-292-2/+21
* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-022-9/+5
* sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans2020-11-106-0/+59
* haswell: Add Intel TXT support in romstageAngel Pons2020-11-045-0/+182
* sec/intel/txt: Add support for running SCLEAN in romstageAngel Pons2020-11-043-0/+186
* sec/intel/txt/Kconfig: Remove the menu for including ACMsArthur Heymans2020-10-281-4/+0
* sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variablesArthur Heymans2020-10-281-10/+11
* sec/intel/txt: Split MTRR setup ASM code into a macroAngel Pons2020-10-222-64/+84
* sec/intel/txt: Add `enable_getsec_or_reset` functionAngel Pons2020-10-222-0/+33
* sec/intel/txt: Extract BIOS ACM loading into a functionAngel Pons2020-10-221-28/+45
* sec/intel/txt: Only run LockConfig for LT-SXAngel Pons2020-10-222-7/+18
* sec/intel/txt: Always run SCHECK on regular bootsAngel Pons2020-10-221-7/+8
* sec/intel/txt: Allow skipping ACM NOP functionAngel Pons2020-10-222-10/+19
* sec/intel/txt/ramstage.c: Do not init the heap on S3 resumeAngel Pons2020-10-221-1/+3
* sec/intel/txt/ramstage.c: Extract heap init into a functionAngel Pons2020-10-221-96/+101
* sec/intel/txt: Add and fill in BIOS Specification infoAngel Pons2020-10-221-0/+8
* sec/intel/txt/common.c: Only log ACM error on failureAngel Pons2020-10-221-2/+0
* sec/intel/txt: Move DPR size to KconfigAngel Pons2020-10-222-1/+10
* intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons2020-10-172-7/+46
* security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]Angel Pons2020-10-171-17/+86
* sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACMAngel Pons2020-10-171-0/+12
* sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPEArthur Heymans2020-10-151-6/+2
* security/intel/txt: Use `smm_region()` to get TSEG baseAngel Pons2020-10-152-5/+16
* security/intel/txt: Add and use DPR register layoutAngel Pons2020-10-122-21/+27
* security/intel/txt: Clean up includesAngel Pons2020-10-126-16/+11
* security/intel/stm: Add options for STM buildEugene Myers2020-10-123-7/+123
* security/intel/txt: Print chipset as hex valueChristian Walter2020-10-081-1/+1
* security/intel/stm: Fix size_t printf format errorFelix Held2020-10-011-1/+1
* security/intel/stm: Fix size_t printf format errorEugene D Myers2020-09-301-1/+1
* src/security: Drop unneeded empty linesElyes HAOUAS2020-09-212-3/+0
* security/intel/txt/getsec.c: Do not check lock bitAngel Pons2020-08-301-1/+1
* security/intel/txt: Add missing definitionsAngel Pons2020-08-301-0/+8
* src: Remove unused 'include <lib.h>'Elyes HAOUAS2020-08-181-1/+0
* security/intel/txt: Fix variable MTRR handlingAngel Pons2020-08-071-48/+47
* security/intel/txt: Allow using CF9 reset, tooAngel Pons2020-08-072-2/+18
* security/intel/txt: Avoid shifting by a negative valueJohn Zhao2020-08-061-0/+3
* security/intel/txt: Add Intel TXT supportPhilipp Deppenwiese2020-07-3110-8/+1824
* security/intel/stm: Add missing <stdbool.h>Angel Pons2020-07-213-0/+3
* src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS2020-07-141-1/+0
* src: Remove unused 'include <lib.h>'Elyes HAOUAS2020-05-181-1/+0
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