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* security/tpm/tss/tcg-1.2/tss.c: Use __func__Elyes HAOUAS2021-01-191-2/+2
* security/intel/stm/StmPlatformSmm.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* security/vboot/secdata_tpm.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi2021-01-152-4/+4
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-142-12/+4
* */Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans2021-01-082-0/+4
* security/intel/txt: Don't run SCHECK on CBnTArthur Heymans2021-01-071-1/+1
* security/intel/txt/ramstage.c: Fix clearing secrets on CBNTArthur Heymans2021-01-041-16/+14
* sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurableArthur Heymans2020-12-292-2/+21
* cbfs: Add verification for RO CBFS metadata hashJulius Werner2020-12-032-12/+13
* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-023-10/+8
* cbfs: Move more stuff into cbfs_boot_lookup()Julius Werner2020-12-022-12/+8
* cbfs: Add metadata cacheJulius Werner2020-11-212-9/+39
* vboot: stop implementing VbExDisplayScreenJoel Kitching2020-11-181-16/+0
* src: Add missing 'include <console/console.h>'Elyes HAOUAS2020-11-171-0/+1
* sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans2020-11-106-0/+59
* security/vboot: Add Kconfig symbol to set hashing block sizeMartin Roth2020-11-062-3/+12
* haswell: Add Intel TXT support in romstageAngel Pons2020-11-045-0/+182
* sec/intel/txt: Add support for running SCLEAN in romstageAngel Pons2020-11-043-0/+186
* sec/intel/txt/Kconfig: Remove the menu for including ACMsArthur Heymans2020-10-281-4/+0
* sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variablesArthur Heymans2020-10-281-10/+11
* security/vboot: fix policy digest for nvmem spacesAndrey Pronin2020-10-281-9/+37
* vboot: Disable vboot functions in SMMJulius Werner2020-10-261-1/+1
* security/tpm/tspi/crtm: Add line break to debug messagesFrans Hendriks2020-10-261-2/+2
* sec/intel/txt: Split MTRR setup ASM code into a macroAngel Pons2020-10-222-64/+84
* sec/intel/txt: Add `enable_getsec_or_reset` functionAngel Pons2020-10-222-0/+33
* sec/intel/txt: Extract BIOS ACM loading into a functionAngel Pons2020-10-221-28/+45
* sec/intel/txt: Only run LockConfig for LT-SXAngel Pons2020-10-222-7/+18
* sec/intel/txt: Always run SCHECK on regular bootsAngel Pons2020-10-221-7/+8
* sec/intel/txt: Allow skipping ACM NOP functionAngel Pons2020-10-222-10/+19
* sec/intel/txt/ramstage.c: Do not init the heap on S3 resumeAngel Pons2020-10-221-1/+3
* sec/intel/txt/ramstage.c: Extract heap init into a functionAngel Pons2020-10-221-96/+101
* sec/intel/txt: Add and fill in BIOS Specification infoAngel Pons2020-10-221-0/+8
* sec/intel/txt/common.c: Only log ACM error on failureAngel Pons2020-10-221-2/+0
* sec/intel/txt: Move DPR size to KconfigAngel Pons2020-10-222-1/+10
* security/vboot: Remove all tpm 1.2 functions for mrc hash in the tpmShelley Chen2020-10-221-70/+41
* mrc_cache: Add tpm_hash_index field to cache_region structShelley Chen2020-10-201-8/+0
* security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEXShelley Chen2020-10-202-10/+40
* security/vboot: Make mrc_cache hash functions genericShelley Chen2020-10-206-59/+73
* mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driverShelley Chen2020-10-201-0/+1
* mrc_cache: Add config MRC_SAVE_HASH_IN_TPMShelley Chen2020-10-202-1/+2
* security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.hShelley Chen2020-10-192-1/+20
* intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons2020-10-172-7/+46
* security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]Angel Pons2020-10-171-17/+86
* sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACMAngel Pons2020-10-171-0/+12
* sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPEArthur Heymans2020-10-151-6/+2
* security/intel/txt: Use `smm_region()` to get TSEG baseAngel Pons2020-10-152-5/+16
* security/intel/txt: Add and use DPR register layoutAngel Pons2020-10-122-21/+27
* security/intel/txt: Clean up includesAngel Pons2020-10-126-16/+11
* security/intel/stm: Add options for STM buildEugene Myers2020-10-123-7/+123
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