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* soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held2022-01-261-3/+1
| | | | | | | | | | | | | | This code is common to at least all Zen-based APUs (Picasso, Cezanne, Sabrina) and is also useful outside of the SoC-specific dynamic ACPI table generation code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Eric Peers <epeers@google.com>
* acpi/acpigen: Constify CST functions' pointersAngel Pons2021-10-191-1/+1
| | | | | | | | | | | | | | The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: add ACPI CPPC support for AMDJulian Schroeder2021-07-151-0/+3
| | | | | | | | | | | | | | This leverages the existing Collaborative Processor Performance Control (CPPC) support and adds CPPC init for AMD/Cezanne. BUG=b:185814875 TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso,stoneyridge/acpi: use defines for MADT parametersFelix Held2021-06-181-6/+5
| | | | | | | | | | | | | | | | Using existing defines instead of magic values improves readability of the code. Also add comments to the MADT IRQ overrides to make it clearer what those actually do. TEST=Timeless build results in identical binary for amd/gardenia (Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add GNB IOAPIC supportFelix Held2021-05-091-1/+2
| | | | | | | | | | | | | | | | | | To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Add support for C-state 3Raul E Rangel2021-04-211-0/+13
| | | | | | | | | | | | | These values match the majolica UEFI firmware. BUG=b:185787242, b:178728116, b:185921043 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If107c7e836942eeba734c1634fa7f8555c3018b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne: Update FADT to support S0i3Jason Glenesk2021-04-161-3/+6
| | | | | | | | | | | | | | | | | Set ACPI_FADT_LOW_PWR_IDLE_S0 flag in FADT. BUG=b:178728116 TEST=Dump FACP and confirm Flags bits match expected. Change-Id: I59ef762a18903135f9daa902ba8d1e40c451e96c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52035 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Port ACPI p-state and c-state entries from picassoJason Glenesk2021-04-161-0/+226
| | | | | | | | | | | | | | | | Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settingsRaul E Rangel2021-02-261-0/+8
| | | | | | | | | | | | | | | | | | | | | With this change NMI works in the kernel: ---------------- | NMI testsuite: -------------------- remote IPI: ok | local IPI: ok | -------------------- Good, all 2 testcases passed! | --------------------------------- See setup_lapic() for where this gets configured. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
* soc/amd/cezanne/acpi: Use IO addresses for ACPI blockRaul E Rangel2021-02-251-13/+9
| | | | | | | | | | | | | | | | | This causes the linux kernel to complain: 32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800 32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804 32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808 32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814 The linux kernel also verifies that the PM Timer block only uses IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: Add FCH IO-APIC to MADTRaul E Rangel2021-02-171-1/+6
| | | | | | | | | | | | | | | | | | TEST=Boot majolica to linux and see IO-APIC logs ACPI: Local APIC address 0xfee00000 ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) ACPI: IRQ0 used by override. ACPI: IRQ9 used by override. Using ACPI (MADT) for SMP configuration information Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib8094c3edf401659d9d740e2cc6266ddd5f91da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: Fill FADT and MADTRaul E Rangel2021-02-141-2/+96
| | | | | | | | | | | | | | | | | | The MADT doesn't populate the IO-APICs yet since we need FSP to configure those. The FADT differs from picasso in the following ways: * The duty_offset is supposed to be 0 * Don't clear x_firmware_ctl_l * Make the extended addresses use MMIO Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: select ACPI support and make the compiler happyFelix Held2021-02-131-0/+20
Follow-up patches will add more functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 06:24:05 +0000