| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/cezanne,picasso: factor out common early non-car cache setup | Felix Held | 2022-01-20 | 1 | -79/+1 |
| * | soc/amd/common/block/espi_util: Refactor eSPI Setup | Karthikeyan Ramasubramanian | 2021-10-13 | 1 | -6/+0 |
| * | soc/amd/cezanne: Init eSPI early if required | Martin Roth | 2021-06-23 | 1 | -0/+6 |
| * | soc/amd/cezanne: call boot_with_psp_timestamp | Kangheui Won | 2021-06-13 | 1 | -0/+7 |
| * | amd/cezanne: verify transfer buffer in bootblock | Kangheui Won | 2021-05-10 | 1 | -0/+7 |
| * | soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry | Felix Held | 2021-02-13 | 1 | -0/+2 |
| * | soc/amd/cezanne: add caching setup in bootblock | Felix Held | 2020-12-13 | 1 | -0/+79 |
| * | soc/amd/cezanne: print APU family and model in bootblock_soc_init | Felix Held | 2020-12-09 | 1 | -0/+3 |
| * | soc/amd/cezanne: add basic early FCH initialization to bootblock | Felix Held | 2020-12-09 | 1 | -0/+3 |
| * | soc/amd/cezanne: call bootblock_main_with_basetime in bootblock_c_entry | Felix Held | 2020-12-09 | 1 | -0/+9 |
| * | soc/amd/cezanne: add skeleton for new SoC | Felix Held | 2020-12-05 | 1 | -0/+18 |
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| Coreboot firmware sources | coreboot |
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