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path: root/src/soc/amd/cezanne/chip.c
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* soc/amd: drop unneeded data_fabric_set_mmio_npFelix Held2024-02-071-1/+1
* soc/amd: commonize PCI root IOAPIC initializationFelix Held2024-02-021-0/+2
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-1/+1
* soc/amd/*/acpi: use common soc_acpi_write_tables prototypeFelix Held2024-01-271-1/+1
* soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tablesFelix Held2024-01-271-1/+1
* soc/amd/*/chip: factor out FSP-S callFelix Held2024-01-201-2/+2
* soc/amd/cezanne/chip: use common data fabric domain resource codeFelix Held2023-06-071-2/+3
* soc/amd: introduce and use common amd_cpu_bus_ops structFelix Held2023-01-171-7/+0
* soc/amd/*/data_fabric: move data_fabric_set_mmio_np to commonFred Reitberger2022-11-031-1/+1
* soc/amd/*: Hook up device_operations in chipset.cbArthur Heymans2022-10-131-47/+2
* soc/amd/*: Move emmc disabling to device opsArthur Heymans2022-10-131-4/+3
* soc/amd/cezanne/chip: add functionality to power down eMMC interfaceFelix Held2021-08-291-0/+6
* soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tablesFelix Held2021-05-051-0/+3
* soc/amd/cezanne: Port ACPI p-state and c-state entries from picassoJason Glenesk2021-04-161-0/+2
* soc/amd/cezanne: Add device tree support for I2CRaul E Rangel2021-04-011-0/+8
* soc/amd/cezanne/chip: add soc_acpi_nameFelix Held2021-02-181-0/+17
* soc/amd/cezanne: add partial data fabric setupFelix Held2021-02-141-0/+3
* soc/amd/cezanne/chip: set device operations for UART MMIO devicesFelix Held2021-02-111-0/+9
* soc/amd/cezanne: add empty mp_init_cpusFelix Held2021-02-111-2/+3
* soc/amd/cezanne/chip: add empty set_mmio_dev_opsFelix Held2021-02-101-0/+7
* soc/amd/cezanne/chip: add empty cpu_bus_opsFelix Held2021-02-101-0/+8
* soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki2021-02-091-2/+1
* soc/amd/cezanne/chip: add PCI bus scanningFelix Held2021-02-071-0/+14
* soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP callsFelix Held2021-01-301-1/+2
* soc/amd/cezanne: add empty ramstage FCH supportFelix Held2021-01-291-0/+4
* soc/amd/cezanne/chip: add FSP silicon init driver callFelix Held2021-01-291-0/+3
* soc/amd/cezanne/chip: add empty SoC device operationsFelix Held2021-01-281-1/+18
* soc/amd/cezanne: add config.c and minimal chip.hFelix Held2020-12-061-0/+1
* soc/amd/cezanne: add skeleton for new SoCFelix Held2020-12-051-0/+5
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 23:02:38 +0000