| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/cezanne,picasso/chipset.cb: drop LAPIC device | Felix Held | 2021-10-22 | 1 | -1/+0 |
| * | soc/amd/cezanne/chip: add functionality to power down eMMC interface | Felix Held | 2021-08-29 | 1 | -0/+1 |
| * | soc/amd/cezanne: Add uart controllers to chipset.cb | Ivy Jian | 2021-04-16 | 1 | -0/+2 |
| * | soc/amd/cezanne: Add i2c controllers to chipset.cb | Mathew King | 2021-03-15 | 1 | -0/+5 |
| * | soc/amd/cezanne: Add USB ports to chipset.cb | Mathew King | 2021-03-10 | 1 | -2/+50 |
| * | soc/amd/cezanne/chipset.cb: clean up and change some aliases | Felix Held | 2021-03-04 | 1 | -24/+24 |
| * | soc/amd/cezanne/chipset.cb: rename alias for SATA controllers | Felix Held | 2021-03-03 | 1 | -2/+2 |
| * | soc/amd/cezanne: Fill out pci devices in chipset.cb | Mathew King | 2021-03-02 | 1 | -9/+49 |
| * | soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices | Felix Held | 2021-02-14 | 1 | -0/+9 |
| * | soc/amd/cezanne: move CPU cluster to chipset device tree | Felix Held | 2021-02-14 | 1 | -0/+3 |
| * | soc/amd/cezzane: Add a minimal chipset tree | Furquan Shaikh | 2021-01-11 | 1 | -0/+5 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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