| Commit message (Collapse) | Author | Age | Files | Lines |
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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If a system doesn't use eSPI or has the eSPI interface already
configured in verstage on PSP, not calling configure_espi_with_mb_hook
from fch_pre_init makes it a bit more obvious that the eSPI interface
initialization will be skipped.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Rename configure_espi to configure_espi_with_mb_hook to clarify that
this function will call into the mb_set_up_early_espi function in the
mainboard-specific code if it exists.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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mb_set_up_early_espi should only be called when
SOC_AMD_COMMON_BLOCK_USE_ESPI is selected.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:194919326
TEST=See SPI settings in bootblock
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When initializing espi early, there may be mainboard requirements to
configure the bus properly. This allows the mainboard to do that.
BUG=192100564
TEST=Build along with next patch, eSPI works on guybrush
Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure
eSPI as early as possible in the x86 boot sequence.
We found that there are situations that can cause the system to hang if
there are any port80h postcodes sent out before eSPI is initialized.
BUG=b:191370340
TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the power state to return to when the power is re-applied
after power failure.
BUG=b:183739671
TEST=Build and Boot to OS in Majolica and Guybrush. By default when the
power fails the device turns on after power is re-applied. When the
POWER_ON_AFTER_POWER_FAILURE is disabled, the device remains off even
after the power is re-applied.
Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52049
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges. Since guybrush is NOT a majolica, this doesn't work very well
there. Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.
BUG=b:183524609
TEST=Set up eSPI on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add I2C initialization in romstage and ramstage.
TEST=To test the I2C connection on Majolica, which doesn't have SPD
connection, call the function below after i2c_soc_init is called.
i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */
It can get the register values of TMP432B.
Or
/* Override EC port in ec.h */
#define EC_DATA 0x662
#define EC_SC 0x666
ec_write(0xA9, 0x40);
i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */
It can get the register values of CM32181A3OP(ALS).
Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add macros, settings and callbacks to support I2C for cezanne.
Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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