| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode | Raul E Rangel | 2022-02-02 | 1 | -0/+7 |
| * | psp_verstage: add new svc for cezanne | Kangheui Won | 2022-02-01 | 1 | -0/+7 |
| * | soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC call | Karthikeyan Ramasubramanian | 2021-09-27 | 1 | -0/+7 |
| * | soc/amd/cezanne: enable crypto in psp_verstage | Kangheui Won | 2021-07-21 | 1 | -0/+14 |
| * | cezanne/psp_verstage: add reset/timer svc | Kangheui Won | 2021-06-07 | 1 | -3/+18 |
| * | psp_verstage: move platform-specific code to chipset.c | Kangheui Won | 2021-05-10 | 1 | -10/+0 |
| * | soc/amd/cezanne: add verstage files | Kangheui Won | 2021-05-02 | 1 | -0/+109 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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