coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/amd/cezanne/psp_verstage: Log the platform boot mode report	Karthikeyan Ramasubramanian	2022-03-10	1	-0/+3
*	soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error	Raul E Rangel	2022-02-16	1	-1/+1
*	soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error	Raul E Rangel	2022-02-12	1	-1/+1
*	soc/amd/cezanne/psp_verstage: Implement get_uart_base	Raul E Rangel	2022-02-08	2	-0/+27
*	soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode	Raul E Rangel	2022-02-02	2	-10/+7
*	psp_verstage: report developer mode to PSP	Kangheui Won	2022-02-01	1	-0/+8
*	psp_verstage: add new svc for cezanne	Kangheui Won	2022-02-01	1	-0/+7
*	psp_verstage: remove psp_ef_table struct	Kangheui Won	2021-10-20	1	-1/+1
*	soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC call	Karthikeyan Ramasubramanian	2021-09-27	1	-0/+7
*	soc/amd/cezanne: enable crypto in psp_verstage	Kangheui Won	2021-07-21	2	-6/+29
*	cezanne/psp_verstage: add reset/timer svc	Kangheui Won	2021-06-07	2	-19/+18
*	psp_verstage: differentiate bios entry	Kangheui Won	2021-05-10	1	-0/+5
*	psp_verstage: move platform-specific code to chipset.c	Kangheui Won	2021-05-10	3	-11/+16
*	cezanne/psp_verstage: clean up duplicated target	Kangheui Won	2021-05-10	1	-3/+0
*	soc/amd/cezanne: add verstage files	Kangheui Won	2021-05-02	4	-0/+214