| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/cezanne: Add support to perform early EC sync | Karthikeyan Ramasubramanian | 2021-04-02 | 1 | -0/+4 |
| * | soc/amd/cezanne: factor out UPD-M configuration from romstage | Felix Held | 2021-03-29 | 1 | -17/+0 |
| * | soc/amd/cezanne: select common APOB NV cache code | Felix Held | 2021-03-10 | 1 | -0/+4 |
| * | soc/amd/cezanne: Disable legacy DMA IO ports | Raul E Rangel | 2021-03-02 | 1 | -0/+4 |
| * | soc/amd: only print CPU family and model in bootblock | Felix Held | 2021-02-25 | 1 | -3/+0 |
| * | soc/amd/cezanne/romstage: Store early dram region | Raul E Rangel | 2021-02-07 | 1 | -0/+3 |
| * | soc/amd/cezanne: populate some FSP-M UPDs | Felix Held | 2021-02-05 | 1 | -0/+11 |
| * | soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls | Felix Held | 2021-01-30 | 1 | -1/+2 |
| * | soc/amd/cezanne: add basic romstage | Felix Held | 2021-01-24 | 1 | -0/+13 |
| * | soc,vendorcode/amd/cezanne: add basic FSP integration | Felix Held | 2021-01-24 | 1 | -0/+5 |
| * | soc/amd/cezanne: add skeleton for new SoC | Felix Held | 2020-12-05 | 1 | -0/+7 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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