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path:
root
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src
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amd
/
cezanne
/
romstage.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
lib/program_loaders.c: Mark run_ramstage with __noreturn
Arthur Heymans
2022-07-14
1
-1
/
+0
*
arch/x86: Add a common romstage entry
Arthur Heymans
2022-06-07
1
-8
/
+3
*
timestamps: Rename timestamps to make names more consistent
Jakub Czapiga
2022-03-08
1
-1
/
+1
*
soc/amd/cezanne: Move APOB update into ramstage
Raul E Rangel
2021-07-14
1
-2
/
+0
*
soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE
Raul E Rangel
2021-06-14
1
-0
/
+4
*
Revert "soc/amd/cezanne: Add support to perform early EC sync"
Karthikeyan Ramasubramanian
2021-04-19
1
-4
/
+0
*
soc/amd/cezanne: save chipset state to CBMEM
Martin Roth
2021-04-14
1
-0
/
+4
*
soc/amd/cezanne: Add support to perform early EC sync
Karthikeyan Ramasubramanian
2021-04-02
1
-0
/
+4
*
soc/amd/cezanne: factor out UPD-M configuration from romstage
Felix Held
2021-03-29
1
-17
/
+0
*
soc/amd/cezanne: select common APOB NV cache code
Felix Held
2021-03-10
1
-0
/
+4
*
soc/amd/cezanne: Disable legacy DMA IO ports
Raul E Rangel
2021-03-02
1
-0
/
+4
*
soc/amd: only print CPU family and model in bootblock
Felix Held
2021-02-25
1
-3
/
+0
*
soc/amd/cezanne/romstage: Store early dram region
Raul E Rangel
2021-02-07
1
-0
/
+3
*
soc/amd/cezanne: populate some FSP-M UPDs
Felix Held
2021-02-05
1
-0
/
+11
*
soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls
Felix Held
2021-01-30
1
-1
/
+2
*
soc/amd/cezanne: add basic romstage
Felix Held
2021-01-24
1
-0
/
+13
*
soc,vendorcode/amd/cezanne: add basic FSP integration
Felix Held
2021-01-24
1
-0
/
+5
*
soc/amd/cezanne: add skeleton for new SoC
Felix Held
2020-12-05
1
-0
/
+7