| Commit message (Collapse) | Author | Age | Files | Lines |
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SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.
BUG=b:216096562
Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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No mainboard in the current tree implements mainboard_i2c_override. In a
follow-up commit the i2c_pad_control struct is introduced to be able to
make more parameters controllable by devicetree settings in the future.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will allow verstage to write post codes.
BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add platform_report_mode function which report current developer mode
status to the PSP. L1 widevine app in the PSP will use this information
to select key box.
BUG=b:211058864
TEST=build and boot guybrush
TEST=build picasso chrome os boards
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This code is common to at least all Zen-based APUs (Picasso, Cezanne,
Sabrina) and is also useful outside of the SoC-specific dynamic ACPI
table generation code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: Eric Peers <epeers@google.com>
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The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Let's increase this to avoid losing any logs.
BUG=b:213828947
TEST=Boot guybrush and no longer see
*** Pre-CBMEM romstage console overflowed, log truncated!
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I393feab8550a7124ab2982ff3d256e3491d27b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This will help debugging verstage failures.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are printed before bootblock
messages.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia60991b3e81c19c24ceb69193840dde873ef3346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since we need the GPIO defines in the devicetree settings, include
gpio.h in each SoC's chip.h file which will indirectly include the
soc-specific soc/gpio.h header instead of having it indirectly included
via soc/i2c.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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uintptr_t is defined in stdint.h which gets included by types.h. I use
types.h instead of stdint.h, since that's also what the Picasso code
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a8c21c462258c8a419ccc3f2db50f74a154e465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.
BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.
Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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S0i3 is a low power state which reduces the power consumption to about
the level of the S3 suspend state where the DRAM is kept in a self-
refresh state and most of the rest of the system is powered down. So
everything that can be switched off in the S0i3 state should be switched
off in order to maximize the standby time.
BUG=b:210722314
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.
BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will
be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this
in PSP.
BUG=b:200578885, b:202397678
BRANCH=None
TEST=Verstage runs during s0i3 resume on Nipperkin
Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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It's already implied by PARALLEL_MP now.
Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit (and thus passing control to OSPM). For ACPI
> only platforms (where SCI_EN is always set), when transitioning from
> either the mechanical off (G3) or soft-off state to the G0 working
> state this register is cleared prior to entering the G0 working state.
This means we don't want to clear the PM1 register on resume. By
clearing it the linux kernel can't correctly increment the wake count
when the power button is pressed. The AMD platforms implement the _SWS
ACPI methods, but the linux kernel doesn't actually use these methods.
BUG=b:172021431
TEST=suspend zork and push power button and verify power button
wake_count increments. Verified other wake sources still work.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states#
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit.
This change makes sure we clear the PM/GPE blocks are cleared before
enabling the SCI_EN bit.
BUG=b:172021431
TEST=Boot guybrush and morphius to OS and verify suspend resume still
works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This part was copied from Picasso but Cezanne has some more bits used so
add the definitions now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.
Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE
clarifies the scope of those definitions. For consistency also add this
prefix to MMIO_DST_FABRIC_ID_SHIFT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register
is bit 12, but that has changed to bit 16 in Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I64c06b84e2c0737b259077e7932f418306638e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Now that CBFS has this functionality built in, we no longer need to
manually code it.
payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.
cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.
In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.
BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds about 30 KiB to FSP-M. When not using the SPI DMA
controller, this change actually has a ~7 ms boot time penalty. When
we use the DMA engine, we end up with about a 5 ms decrease. Once we
switch to 100 MHz SPI this will help even more since we have effectively
eliminated the decompression time.
BUG=b:179699789
TEST=Boot nipperkin to OS and take boot time measurements
fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed)
fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed)
- FSP-M / no async -
| 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) |
...
| 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) |
- FSP-M / async -
| 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) |
...
| 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) |
| 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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This change increases the fsps.bin by 20 KiB, but it decreases
decompression time. When not using preloading we save about 4 ms, when
using preloading we save about 6.
BUG=b:179699789
TEST=Boot nipperkin to OS
fsps.bin 0x4afc0 fsp 66253 LZMA (200704 decompressed)
fsps.bin 0x45fc0 fsp 87157 LZ4 (200704 decompressed)
- FSP-S / no async -
| 505 - starting to verify keyblock/preamble (RSA) | 9.36 | 11.012 Δ( 1.65, 0.11%) |
...
| 971 - loading FSP-S | 7.095 | 6.141 Δ( -0.95, -0.07%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.008 Δ( -0.00, -0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 15.149 | 8.98 Δ( -6.17, -0.42%) |
| 954 - calling FspSiliconInit | 0.038 | 0.037 Δ( -0.00, -0.00%) |
- FSP-S / async -
| 508 - finished loading body | 177.978 | 179.689 Δ( 1.71, 0.12%) |
...
| 971 - loading FSP-S | 6.928 | 7.225 Δ( 0.30, 0.02%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.011 | 0.01 Δ( -0.00, -0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 8.312 | 0.241 Δ( -8.07, -0.58%) |
| 954 - calling FspSiliconInit | 0.091 | 0.09 Δ( -0.00, -0.00%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.
BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) |
| 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) |
| 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) |
| 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) |
| 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) |
| 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) |
CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Since the if block contains multiple statements, it uses curly braces
around them, so also add curly braces around the else block even though
it only contains one statement.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use bitwise or instead of additions to build bit masks with multiple
bits set.
TEST=Timeless build results in identical image on amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16
of the misc I2C pad control registers is defined as BiasCrtEn, so rename
I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We no longer need to do this since we relocate at runtime.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was
derived by examining the `cbfstool print` output and summing the files
we intend to preload.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.
BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Since all other defines for the number of certain things are at the top
of the file, move NUMBER_SMITYPES there as well to keep things
consistent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap
returns early when the scimap is greater or equal than SCIMAPS, so for
SMITYPE_ACDC_TIMER it returned early without doing what was expected
from it to do despite that being a valid value, so fix this off-by-one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS.
BUG=b:179699789
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed
that the native function names don't have the EMMC_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This makes this header file consistent with the rest.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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