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* soc/amd/common/block/acpi/bert: fix NULL checkFelix Held2021-06-161-1/+1
* soc/amd/cezanne/include/soc/iomap: add eMMC MMIO base addressesFelix Held2021-06-161-0/+3
* soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNTFelix Held2021-06-162-4/+2
* soc/amd/cezanne/acpi/mmio: use AOAC offset definesFelix Held2021-06-161-6/+7
* soc/amd/cezanne: factor out AOAC offset definesFelix Held2021-06-164-14/+23
* soc/amd/picasso/acpi/sb_fch: use AOAC offset definesFelix Held2021-06-161-6/+7
* soc/amd/picasso: factor out AOAC offset definesFelix Held2021-06-164-13/+21
* soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controllerFelix Held2021-06-162-0/+2
* soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGERaul E Rangel2021-06-142-0/+8
* soc/amd/common/pi/agesawrapper: use IOAPIC ID definesFelix Held2021-06-141-3/+3
* soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski2021-06-131-0/+1
* soc/amd/picasso: Move Type 17 DMI generation to commonNikolai Vyssotski2021-06-135-2/+6
* soc/amd/cezanne: call boot_with_psp_timestampKangheui Won2021-06-131-0/+7
* soc/amd/cezanne: remove warm reset flag codeFelix Held2021-06-114-19/+0
* soc/amd/stoneyridge: Set missing RTC offsets for day alarm and centuryAnand K Mistry2021-06-111-3/+3
* cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki2021-06-113-3/+3
* soc/amd: factor out acpi_soc_get_bert_region to amd/commonFelix Held2021-06-084-40/+26
* soc/amd/picasso/agesa_acpi: add BERT supportFelix Held2021-06-081-0/+20
* soc/amd/stoneyridge: use common BERT ACPI table generationFelix Held2021-06-081-21/+19
* arch/x86/include/bert_storage: introduce bert_should_generate_acpi_tableFelix Held2021-06-081-1/+1
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-073-3/+0
* soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski2021-06-071-5/+9
* soc/amd/cezanne: Configure I2C Pad RX Select through devicetreeKarthikeyan Ramasubramanian2021-06-072-1/+6
* cezanne/psp_verstage: add reset/timer svcKangheui Won2021-06-073-21/+20
* psp_verstage: initialize i2c in soc_initKangheui Won2021-06-071-0/+6
* soc/amd/picasso: remove warm reset flag codeFelix Held2021-06-025-50/+28
* soc/amd/cezanne/include/iomap: properly align definesFelix Held2021-06-011-1/+1
* soc/amd/picasso: introduce and use chipset device treeFelix Held2021-06-012-0/+50
* soc/amd/cezanne: Add pre-FSPM call to the mainboardMartin Roth2021-05-312-0/+7
* soc/amd/common/block/espi: Explicitly assert PLTRST#Raul E Rangel2021-05-301-4/+11
* soc/amd/picasso: fix MCACHE on psp_verstage RO bootKangheui Won2021-05-282-1/+10
* soc/amd/common/block: Fix missing include in acp.hRaul E Rangel2021-05-272-1/+3
* soc/amd/picasso: add devicetree setting for PSPP policyFelix Held2021-05-272-0/+10
* soc/amd/cezanne: add devicetree setting for PSPP policyFelix Held2021-05-272-0/+10
* soc/amd/picasso/mca: use MCAX registers instead of legacy MCAFelix Held2021-05-261-10/+14
* soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder2021-05-262-0/+9
* soc/amd/common/block/espi: Fix typo in espi_setup_periph_channelRaul E Rangel2021-05-261-2/+2
* soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10msRaul E Rangel2021-05-251-1/+1
* soc/amd: reduce MCACHE size with psp_verstageKangheui Won2021-05-222-0/+8
* soc/amd/cezanne,picasso/reset: use byte I/O read for NCP_ERRFelix Held2021-05-222-2/+2
* soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held2021-05-213-17/+3
* soc/amd/common: Show espi init in logMartin Roth2021-05-201-0/+4
* soc/amd/common/block/espi_util: Work around in-band reset race conditionRaul E Rangel2021-05-191-2/+30
* soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settingsFelix Held2021-05-193-0/+69
* soc/amd/picasso: move gpp_clk_req_setting definition to chip.hFelix Held2021-05-192-9/+8
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-2/+0
* soc/amd/*/Makefile.inc: Strip the quotesZheng Bao2021-05-162-2/+2
* soc/amd/cezanne: Enable GFX HDA FSP UPDKarthikeyan Ramasubramanian2021-05-141-0/+26
* soc/amd: factor out acpigen_write_alib_dptc to common codeFelix Held2021-05-134-45/+33
* soc/amd/cezanne/root_complex: generate DPTC ACPI methodFelix Held2021-05-132-0/+76
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 18:54:20 +0000