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path: root/src/soc/cavium/cn81xx/soc.c
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* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-021-2/+1
* src: Remove unused 'include <bootmode.h>'Elyes HAOUAS2020-06-021-1/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber2020-04-101-1/+1
* Drop unnecessary DEVICE_NOOP entriesNico Huber2020-04-101-1/+0
* soc/cavium: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-12/+3
* Drop explicit NULL initializations from `device_operations`Elyes HAOUAS2020-04-051-1/+0
* soc: Remove copyright noticesPatrick Georgi2020-03-181-2/+0
* arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner2019-09-141-2/+2
* device_tree: Make FDT property data non-constJulius Werner2019-06-041-1/+1
* device_tree: Have absolute paths start with '/'Julius Werner2019-06-041-5/+5
* device_tree: Drop sub-node path lookup from dt_find_node_by_path()Julius Werner2019-06-041-5/+5
* device_tree: Add phandle caching and lookupsJulius Werner2019-06-041-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-2/+2
* drivers/cavium: Add UART PCI driverPatrick Rudolph2019-02-221-12/+0
* bootmem: add new memory type for BL31Ting Shen2019-02-051-7/+0
* src: Get rid of duplicated includesElyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* soc/cavium: dynamic UART initialization for cavium cn8100Jens Drenhaus2018-10-101-0/+28
* soc/cavium/cn81xx: Don't use device_t in ramstageElyes HAOUAS2018-09-181-4/+4
* soc/cavium/cn81xx: Don't directly manipulate devicetree dataPatrick Rudolph2018-08-241-4/+16
* device_tree/fit: Constify data structuresPatrick Rudolph2018-08-241-8/+9
* soc/cavium/cn81xx: Fix minor thingsPatrick Rudolph2018-08-101-1/+2
* [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usablePatrick Rudolph2018-08-101-1/+2
* soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph2018-07-301-3/+53
* soc/cavium: Apply additional devicetree fixupsPatrick Rudolph2018-07-231-0/+269
* soc/cavium: Add PCI supportPatrick Rudolph2018-07-191-1/+7
* soc/cavium: Add secondary CPU supportPatrick Rudolph2018-07-101-3/+6
* cavium: Add CN81xx SoC and eval board supportDavid Hendricks2018-07-101-0/+65
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