coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/alderlake: Add minimal ACPI support for PEG ports	Tim Wawrzynczak	2022-01-06	1	-0/+3
*	soc/intel/alderlake: Add igd device	Wisley Chen	2021-09-16	1	-0/+1
*	soc/intel/alderlake: Add support for I2C6 and I2C7	Varshit B Pandya	2021-07-20	1	-0/+2
*	soc/intel/alderlake: Enable support for common IRQ block	Tim Wawrzynczak	2021-06-29	1	-1/+16
*	soc/intel: Replace open-coded buffer length calculation	Angel Pons	2021-04-21	1	-4/+2
*	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	Subrata Banik	2021-03-27	1	-1/+1
*	soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore	Aamir Bohra	2021-02-24	1	-8/+0
*	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki	2021-02-09	1	-2/+1
*	soc/intel/alderlake: Update PCH and CPU PCIe RP table	Eric Lai	2021-01-18	1	-7/+2
*	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner	2020-12-30	1	-0/+3
*	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik	2020-10-03	1	-0/+191