| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/alderlake: Log CSE RO write protection info for ADL | Sridhar Siricilla | 2022-03-30 | 1 | -0/+23 |
| * | soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode | Subrata Banik | 2022-01-02 | 1 | -2/+2 |
| * | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik | 2020-10-03 | 1 | -0/+167 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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