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path: root/src/soc/intel/alderlake/meminit.c
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* soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski2023-08-031-1/+1
* soc/intel/alderlake: Allow channel 0 for DDR5 memory-downJeremy Soller2023-07-311-2/+2
* soc/intel/alderlake: Hook up CsPiStartHighinEct UPDKane Chen2023-07-181-0/+3
* soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford2023-03-041-2/+2
* soc/intel/alderlake: Fix DDR5 channel mappingAngel Pons2022-08-121-8/+6
* soc/intel/alderlake: Configure DDR5 Physical channel width to 64Meera Ravindranath2022-08-021-1/+1
* {mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik2022-03-151-2/+2
* soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik2022-03-151-2/+2
* {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik2022-03-151-1/+2
* mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee2022-03-021-2/+3
* soc/intel/alderlake: Make clang static assert happyArthur Heymans2022-02-211-2/+4
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-131-26/+26
* soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath2021-07-131-0/+27
* soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik2021-05-161-5/+6
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar2021-05-161-8/+8
* soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela2021-05-101-0/+6
* soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik2021-03-261-2/+12
* soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik2021-03-261-3/+2
* soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh2021-01-251-155/+210
* soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla2020-11-291-0/+1
* mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik2020-10-291-0/+1
* soc/intel/alderlake/romstage: Do initial SoC commit till romstageSubrata Banik2020-09-151-0/+183
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