| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/alderlake: Use PMC IPC to disable HECI1 | Subrata Banik | 2022-02-02 | 1 | -17/+0 |
| * | soc/intel/common/cse: Rework heci_disable function | Subrata Banik | 2022-02-02 | 1 | -1/+1 |
| * | soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config | Subrata Banik | 2022-01-25 | 1 | -4/+3 |
| * | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen | 2021-05-07 | 1 | -0/+8 |
| * | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik | 2020-10-03 | 1 | -0/+40 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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